project-oberon-risc5-architecture.txt (5704B)
1 Project Oberon RISC5 Architecture 2 --------------------------------- 3 4 The various documents describing Project Oberon's RISC5 architecture 5 are not entirely in agreement with each other, and (maybe most critically) 6 not entirely in agreement with the verilog implementation of the CPU 7 is RISC.v. This document attempts to be the "most correct" version, 8 looking to the verilog implementation RISC.v as "most authoritative" 9 10 0. Processor Resources 11 ---------------------- 12 13 Program Counter PC 14 General Registers R0..R15 15 Flag Bits N C V Z 16 Mul/Div Result Reg H 17 Special Irq Reg SPC captures NCVZ, PC on IRQ, restores on RTI 18 Memory Mem[] byte or word addressible main memory 19 20 R12 is known as MT, the Module Table pointer (system globals) 21 R13 is known as SB, the Static Base pointer (module globals) 22 R14 is known as SP, the Stack Pointer 23 R15 is known as LNK, the Link Register 24 25 The first three are Project Oberon software conventions and have 26 no special meaning in hardware. R15 is where branch-with-link 27 instructions store the return address. 28 29 1. Register Instructions (F0 & F1) 30 ---------------------------------- 31 4 4 4 4 4 4 32 +------+-------+-------+-------+-------------+-------+-------+ 33 F0 | 00u0 | a | b | op | | 0000 | c | 34 +------+-------+-------+-------+-------------+-------+-------+ 35 n=Rc 36 37 4 4 4 4 16 38 +------+-------+-------+-------+-----------------------------+ 39 F1 | 01uv | a | b | op | i | 40 +------+-------+-------+-------+-----------------------------+ 41 v=0: n = i, v=1: n = 0xFFFF0000 | i 42 43 0 MOV a, n Ra = n 44 1 LSL a, b, n Ra = Rb << n (shift left) 45 2 ASR a, b, n Ra = Rb >> n (sight right, sign extending) 46 3 ROR a, b, n Ra = Rb rot n (rotate right) 47 4 AND a, b, n Ra = Rb & n logical operations 48 5 ANN a, b, n Ra = Rb & ~n 49 6 IOR a, b, n Ra = Rb | n 50 7 XOR a, b, n Ra = Rb ^ n 51 8 ADD a, b, n Ra = Rb + n integer arithmetic 52 9 SUB a, b, n Ra = Rb - n 53 10 MUL a, b, n Ra = Rb * n H = result high 32 bits 54 11 DIV a, b, n Ra = Rb / n H = remainder 55 12 FAD a, b, n Ra = Rb + n floating point arithmetic 56 13 FSB a, b, n Ra = Rb - n 57 14 FML a, b, n Ra = Rb * n 58 15 FDV a, b, n Ra = Rb / n 59 60 u=1 modifies some ops: 61 0 MOV a, H Ra = H v=0 62 0 MOV a, NZCV Ra = (NZCV<<28)|INFO) v=1 63 0 MHI a, n Ra = n << 16 64 8 ADC a, b, n Ra = Rb + n + C 65 9 SBC a, b, n Ra = Rb - n - C 66 10 UMUL a, b, n Ra = Rb * n (unsigned multiply) 67 68 INFO is 0x0000053 on the 2018 FPGA RISC5 implementation. 69 70 1a. Flag Bits 71 ------------- 72 73 N and Z are set on *any* register write (arithmetic or load) 74 75 C and V are set on integer ADD or SUB operations. 76 77 78 2. Memory Instructions (F2) 79 --------------------------- 80 4 4 4 20 81 +------+-------+-------+-------------------------------------+ 82 F2 | 10uv | a | b | off | 83 +------+-------+-------+-------------------------------------+ 84 u=0: load, u=1: store v=0: word, v=1: byte 85 86 LD a, b, off Ra = Mem[Rb + signext32(off)] 87 ST a, b, off Mem[Rb + signext32(off)] = Ra 88 89 3. Branch Instructions (F3) 90 --------------------------- 91 4 4 4 4 92 +------+-------+-----------------------------+-------+-------+ 93 F3 | 110v | cond | | 0000 | c | 94 +------+-------+-----------------------------+-------+-------+ 95 4 4 24 96 +------+-------+---------------------------------------------+ 97 F3 | 111v | cond | off | 98 +------+-------+---------------------------------------------+ 99 v=0: no link, v=1: link 100 101 B<cond> c PC = Rc (low two bits 0'd) 102 BL<cond> c R15 = PC + 4, PC = Rc (low two bits 0'd) 103 B<cond> off PC = PC + 4 + signext32(off) * 4 104 BL<cond> off R15 = PC + 4, PC = PC + 4 + signext32(off) * 4 105 106 0000 MI negative (minus) N 1000 PL positive ~N 107 0001 EQ equal (zero) Z 1001 NE not equal ~Z 108 0010 CS carry set C 1010 CC carry clear ~C 109 0011 VS overflow set V 1011 VC overflow clear ~V 110 0100 LS less or same C|Z 1100 HI high ~(C|Z) 111 0101 LT less than (N^V) 1101 GE greater or equal ~(N^V) 112 0110 LE less or equal (N^V)|Z 1110 GT greater than ~(N^V)|Z 113 0111 always T 1111 never F 114 115 116 4. Interrupts (Special F3 Encodings) 117 ------------------------------------ 118 4 4 4 4 119 +------+-------+-----------------------------+-------+-------+ 120 F3 | 1100 | 0111 | | 0001 | xxxx | 121 +------+-------+-----------------------------+-------+-------+ 122 RTI Return from IRQ, restoring PC and Flags 123 124 4 4 4 4 125 +------+-------+-----------------------------+-------+-------+ 126 F3 | 1100 | 1111 | | 0010 | 000e | 127 +------+-------+-----------------------------+-------+-------+ 128 STI set irq enable, allowing irqs (e=1) 129 CLI clear irq enable, masking irqs (e=0) 130 131 On interrupt, the flags and PC are saved and execution continues 132 at address 0x00000004. 133 134 On RTI, the flags and PC are restored. 135 136 The H register is neither saved nor restored (MUL/DIV during an 137 irq handler is thus unsafe).