cpu32

verilog 32bit cpu experiment
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de0board.v (2679B)


      1 // Copyright 2012, Brian Swetland
      2 
      3 module de0board(
      4 	input CLOCK_50,
      5 	output [9:0] LEDG,
      6 	output [6:0] HEX0_D,
      7 	output [6:0] HEX1_D,
      8 	output [6:0] HEX2_D,
      9 	output [6:0] HEX3_D,
     10 	output HEX0_DP,
     11 	output HEX1_DP,
     12 	output HEX2_DP,
     13 	output HEX3_DP,
     14 	output [3:0] VGA_R,
     15 	output [3:0] VGA_G,
     16 	output [3:0] VGA_B,
     17 	output VGA_HS,
     18 	output VGA_VS
     19 	);
     20 
     21 wire [15:0] status;
     22 reg [31:0] count;
     23 
     24 assign LEDG = 10'b1111111111;
     25 assign HEX0_DP = ~reset;
     26 assign HEX1_DP = 1'b1;
     27 assign HEX2_DP = 1'b1;
     28 assign HEX3_DP = 1'b1;
     29 
     30 hex2seven hex0(.in(status[3:0]),.out(HEX0_D));
     31 hex2seven hex1(.in(status[7:4]),.out(HEX1_D));
     32 hex2seven hex2(.in(status[11:8]),.out(HEX2_D));
     33 hex2seven hex3(.in(status[15:12]),.out(HEX3_D));
     34 
     35 wire clk, reset;
     36 assign clk = CLOCK_50;
     37 
     38 reg clk25;
     39 
     40 always @(posedge clk)
     41 	clk25 = ~clk25;
     42 
     43 always @(posedge clk)
     44 	count <= count + 1;
     45 
     46 wire newline, advance;
     47 wire [11:0] pixel;
     48 wire [10:0] vram_addr;
     49 wire [7:0] vram_data;
     50 wire [7:0] line;
     51 
     52 wire [31:0] jtag_addr, jtag_data;
     53 wire jtag_we;
     54 
     55 vga vga(
     56 	.clk(clk25),
     57 	.reset(1'b0),
     58 	.newline(newline),
     59 	.advance(advance),
     60 	.line(line),
     61 	.pixel(pixel),
     62 	.r(VGA_R),
     63 	.b(VGA_B),
     64 	.g(VGA_G),
     65 	.hs(VGA_HS),
     66 	.vs(VGA_VS)
     67 	);
     68 
     69 pixeldata pxd(
     70 	.clk(clk25),
     71 	.newline(newline),
     72 	.advance(advance),
     73 	.line(line),
     74 	.pixel(pixel),
     75 	.vram_data(vram_data),
     76 	.vram_addr(vram_addr)
     77 	);
     78 	
     79 //assign status = count[31:16];
     80 assign status = d_addr[15:0];
     81 
     82 wire [31:0] romaddr, romdata;
     83 wire [31:0] d_addr, d_data_r, d_data_w;
     84 wire d_we;
     85 
     86 videoram #(8,11) vram(
     87 	.clk(clk),
     88 	.we(d_we && (d_addr[31:16] == 16'hA000)),
     89 	.rdata(vram_data),
     90 	.raddr(vram_addr),
     91 	.wdata(d_data_w[7:0]),
     92 	.waddr(d_addr[13:2]),
     93 	);
     94 
     95 dualsyncram #(32,12) memory(
     96 	.clk(clk),
     97 	.a_addr(jtag_we ? jtag_addr[13:2] : romaddr[13:2]),
     98 	.a_rdata(romdata),
     99 	.a_wdata(jtag_data),
    100 	.a_we(jtag_we),
    101 	.b_addr(d_addr[13:2]),
    102 	.b_rdata(d_data_r),
    103 	.b_wdata(d_data_w),
    104 	.b_we(d_we && (d_addr[31:14] == 20'd0))
    105 	);
    106 
    107 cpu32 cpu(
    108 	.clk(clk),
    109 	.reset(reset),
    110 	.i_addr(romaddr),
    111 	.i_data(romdata),
    112 	.d_data_r(d_data_r),
    113 	.d_data_w(d_data_w),
    114 	.d_addr(d_addr),
    115 	.d_data_we(d_we)
    116 	);
    117 
    118 jtagloader loader(
    119 	.clk(clk),
    120 	.addr(jtag_addr),
    121 	.data(jtag_data),
    122 	.we(jtag_we),
    123 	.reset(reset)
    124 	);
    125 
    126 endmodule
    127 
    128 module hex2seven(
    129 	input [3:0] in,
    130 	output reg [6:0] out
    131 	);
    132 
    133 always @(*) case (in)
    134 	4'h0: out = 7'b1000000;
    135 	4'h1: out = 7'b1111001;
    136 	4'h2: out = 7'b0100100;
    137 	4'h3: out = 7'b0110000;
    138 	4'h4: out = 7'b0011001;
    139 	4'h5: out = 7'b0010010;
    140 	4'h6: out = 7'b0000011;
    141 	4'h7: out = 7'b1111000;
    142 	4'h8: out = 7'b0000000;
    143 	4'h9: out = 7'b0011000;
    144 	4'hA: out = 7'b0001000;
    145 	4'hB: out = 7'b0000011;
    146 	4'hC: out = 7'b1000110;
    147 	4'hD: out = 7'b0100001;
    148 	4'hE: out = 7'b0000110;
    149 	4'hF: out = 7'b0001110;
    150 endcase
    151 
    152 endmodule