jtag.v (6927B)
1 // megafunction wizard: %Virtual JTAG% 2 // GENERATION: STANDARD 3 // VERSION: WM1.0 4 // MODULE: sld_virtual_jtag 5 6 // ============================================================ 7 // File Name: jtag.v 8 // Megafunction Name(s): 9 // sld_virtual_jtag 10 // 11 // Simulation Library Files(s): 12 // altera_mf 13 // ============================================================ 14 // ************************************************************ 15 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 // 17 // 11.1 Build 173 11/01/2011 SJ Web Edition 18 // ************************************************************ 19 20 21 //Copyright (C) 1991-2011 Altera Corporation 22 //Your use of Altera Corporation's design tools, logic functions 23 //and other software and tools, and its AMPP partner logic 24 //functions, and any output files from any of the foregoing 25 //(including device programming or simulation files), and any 26 //associated documentation or information are expressly subject 27 //to the terms and conditions of the Altera Program License 28 //Subscription Agreement, Altera MegaCore Function License 29 //Agreement, or other applicable license agreement, including, 30 //without limitation, that your use is for the sole purpose of 31 //programming logic devices manufactured by Altera and sold by 32 //Altera or its authorized distributors. Please refer to the 33 //applicable agreement for further details. 34 35 36 // synopsys translate_off 37 `timescale 1 ps / 1 ps 38 // synopsys translate_on 39 module jtag ( 40 ir_out, 41 tdo, 42 ir_in, 43 tck, 44 tdi, 45 virtual_state_cdr, 46 virtual_state_cir, 47 virtual_state_e1dr, 48 virtual_state_e2dr, 49 virtual_state_pdr, 50 virtual_state_sdr, 51 virtual_state_udr, 52 virtual_state_uir); 53 54 input [3:0] ir_out; 55 input tdo; 56 output [3:0] ir_in; 57 output tck; 58 output tdi; 59 output virtual_state_cdr; 60 output virtual_state_cir; 61 output virtual_state_e1dr; 62 output virtual_state_e2dr; 63 output virtual_state_pdr; 64 output virtual_state_sdr; 65 output virtual_state_udr; 66 output virtual_state_uir; 67 68 wire sub_wire0; 69 wire sub_wire1; 70 wire [3:0] sub_wire2; 71 wire sub_wire3; 72 wire sub_wire4; 73 wire sub_wire5; 74 wire sub_wire6; 75 wire sub_wire7; 76 wire sub_wire8; 77 wire sub_wire9; 78 wire sub_wire10; 79 wire virtual_state_cir = sub_wire0; 80 wire virtual_state_pdr = sub_wire1; 81 wire [3:0] ir_in = sub_wire2[3:0]; 82 wire tdi = sub_wire3; 83 wire virtual_state_udr = sub_wire4; 84 wire tck = sub_wire5; 85 wire virtual_state_e1dr = sub_wire6; 86 wire virtual_state_uir = sub_wire7; 87 wire virtual_state_cdr = sub_wire8; 88 wire virtual_state_e2dr = sub_wire9; 89 wire virtual_state_sdr = sub_wire10; 90 91 sld_virtual_jtag sld_virtual_jtag_component ( 92 .ir_out (ir_out), 93 .tdo (tdo), 94 .virtual_state_cir (sub_wire0), 95 .virtual_state_pdr (sub_wire1), 96 .ir_in (sub_wire2), 97 .tdi (sub_wire3), 98 .virtual_state_udr (sub_wire4), 99 .tck (sub_wire5), 100 .virtual_state_e1dr (sub_wire6), 101 .virtual_state_uir (sub_wire7), 102 .virtual_state_cdr (sub_wire8), 103 .virtual_state_e2dr (sub_wire9), 104 .virtual_state_sdr (sub_wire10) 105 // synopsys translate_off 106 , 107 .jtag_state_cdr (), 108 .jtag_state_cir (), 109 .jtag_state_e1dr (), 110 .jtag_state_e1ir (), 111 .jtag_state_e2dr (), 112 .jtag_state_e2ir (), 113 .jtag_state_pdr (), 114 .jtag_state_pir (), 115 .jtag_state_rti (), 116 .jtag_state_sdr (), 117 .jtag_state_sdrs (), 118 .jtag_state_sir (), 119 .jtag_state_sirs (), 120 .jtag_state_tlr (), 121 .jtag_state_udr (), 122 .jtag_state_uir (), 123 .tms () 124 // synopsys translate_on 125 ); 126 defparam 127 sld_virtual_jtag_component.sld_auto_instance_index = "NO", 128 sld_virtual_jtag_component.sld_instance_index = 0, 129 sld_virtual_jtag_component.sld_ir_width = 4, 130 sld_virtual_jtag_component.sld_sim_action = "", 131 sld_virtual_jtag_component.sld_sim_n_scan = 0, 132 sld_virtual_jtag_component.sld_sim_total_length = 0; 133 134 135 endmodule 136 137 // ============================================================ 138 // CNX file retrieval info 139 // ============================================================ 140 // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" 141 // Retrieval info: PRIVATE: show_jtag_state STRING "0" 142 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 143 // Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "NO" 144 // Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "0" 145 // Retrieval info: CONSTANT: SLD_IR_WIDTH NUMERIC "4" 146 // Retrieval info: CONSTANT: SLD_SIM_ACTION STRING "" 147 // Retrieval info: CONSTANT: SLD_SIM_N_SCAN NUMERIC "0" 148 // Retrieval info: CONSTANT: SLD_SIM_TOTAL_LENGTH NUMERIC "0" 149 // Retrieval info: USED_PORT: ir_in 0 0 4 0 OUTPUT NODEFVAL "ir_in[3..0]" 150 // Retrieval info: USED_PORT: ir_out 0 0 4 0 INPUT NODEFVAL "ir_out[3..0]" 151 // Retrieval info: USED_PORT: tck 0 0 0 0 OUTPUT NODEFVAL "tck" 152 // Retrieval info: USED_PORT: tdi 0 0 0 0 OUTPUT NODEFVAL "tdi" 153 // Retrieval info: USED_PORT: tdo 0 0 0 0 INPUT NODEFVAL "tdo" 154 // Retrieval info: USED_PORT: virtual_state_cdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_cdr" 155 // Retrieval info: USED_PORT: virtual_state_cir 0 0 0 0 OUTPUT NODEFVAL "virtual_state_cir" 156 // Retrieval info: USED_PORT: virtual_state_e1dr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_e1dr" 157 // Retrieval info: USED_PORT: virtual_state_e2dr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_e2dr" 158 // Retrieval info: USED_PORT: virtual_state_pdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_pdr" 159 // Retrieval info: USED_PORT: virtual_state_sdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_sdr" 160 // Retrieval info: USED_PORT: virtual_state_udr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_udr" 161 // Retrieval info: USED_PORT: virtual_state_uir 0 0 0 0 OUTPUT NODEFVAL "virtual_state_uir" 162 // Retrieval info: CONNECT: @ir_out 0 0 4 0 ir_out 0 0 4 0 163 // Retrieval info: CONNECT: @tdo 0 0 0 0 tdo 0 0 0 0 164 // Retrieval info: CONNECT: ir_in 0 0 4 0 @ir_in 0 0 4 0 165 // Retrieval info: CONNECT: tck 0 0 0 0 @tck 0 0 0 0 166 // Retrieval info: CONNECT: tdi 0 0 0 0 @tdi 0 0 0 0 167 // Retrieval info: CONNECT: virtual_state_cdr 0 0 0 0 @virtual_state_cdr 0 0 0 0 168 // Retrieval info: CONNECT: virtual_state_cir 0 0 0 0 @virtual_state_cir 0 0 0 0 169 // Retrieval info: CONNECT: virtual_state_e1dr 0 0 0 0 @virtual_state_e1dr 0 0 0 0 170 // Retrieval info: CONNECT: virtual_state_e2dr 0 0 0 0 @virtual_state_e2dr 0 0 0 0 171 // Retrieval info: CONNECT: virtual_state_pdr 0 0 0 0 @virtual_state_pdr 0 0 0 0 172 // Retrieval info: CONNECT: virtual_state_sdr 0 0 0 0 @virtual_state_sdr 0 0 0 0 173 // Retrieval info: CONNECT: virtual_state_udr 0 0 0 0 @virtual_state_udr 0 0 0 0 174 // Retrieval info: CONNECT: virtual_state_uir 0 0 0 0 @virtual_state_uir 0 0 0 0 175 // Retrieval info: GEN_FILE: TYPE_NORMAL jtag.v TRUE 176 // Retrieval info: GEN_FILE: TYPE_NORMAL jtag.inc FALSE 177 // Retrieval info: GEN_FILE: TYPE_NORMAL jtag.cmp FALSE 178 // Retrieval info: GEN_FILE: TYPE_NORMAL jtag.bsf FALSE 179 // Retrieval info: GEN_FILE: TYPE_NORMAL jtag_inst.v FALSE 180 // Retrieval info: GEN_FILE: TYPE_NORMAL jtag_bb.v FALSE 181 // Retrieval info: LIB_FILE: altera_mf