jtagloader.v (1123B)
1 // Copyright 2012, Brian Swetland 2 3 `timescale 1ns/1ns 4 5 module jtagloader( 6 input clk, 7 output we, 8 output reg [31:0] addr, 9 output [31:0] data, 10 output reg reset 11 ); 12 13 parameter IR_CTRL = 4'd0; 14 parameter IR_ADDR = 4'd1; 15 parameter IR_DATA = 4'd2; 16 17 initial reset = 0; 18 19 wire update; 20 wire [3:0] iir; 21 wire tck, tdi, sdr, udr, uir; 22 reg [31:0] dr; 23 reg [3:0] ir; 24 25 jtag jtag0( 26 .tdi(tdi), 27 .tdo(dr[0]), 28 .tck(tck), 29 .ir_in(iir), 30 .virtual_state_sdr(sdr), 31 .virtual_state_udr(udr), 32 .virtual_state_uir(uir) 33 ); 34 35 always @(posedge tck) begin 36 if (uir) ir <= iir; 37 if (sdr) dr <= { tdi, dr[31:1] }; 38 end 39 40 sync sync0( 41 .in(udr), 42 .clk_in(tck), 43 .out(update), 44 .clk_out(clk) 45 ); 46 47 assign data = dr; 48 assign we = update & (ir == IR_DATA); 49 50 always @(posedge clk) 51 if (update) case (iir) 52 IR_CTRL: reset <= dr[0]; 53 IR_ADDR: addr <= dr; 54 IR_DATA: addr <= addr + 32'd4; 55 endcase 56 57 endmodule 58 59 module sync( 60 input clk_in, 61 input clk_out, 62 input in, 63 output out 64 ); 65 reg toggle; 66 reg [2:0] sync; 67 always @(posedge clk_in) 68 if (in) toggle <= ~toggle; 69 always @(posedge clk_out) 70 sync <= { sync[1:0], toggle }; 71 assign out = (sync[2] ^ sync[1]); 72 endmodule 73