de0nano.v (1577B)
1 module de0nano( 2 input CLOCK_50, 3 output [7:0] LED, 4 input [1:0] KEY, 5 input [3:0] SW, 6 7 output [12:0] DRAM_ADDR, 8 output [1:0] DRAM_BA, 9 output DRAM_CAS_N, 10 output DRAM_CKE, 11 output DRAM_CLK, 12 output DRAM_CS_N, 13 inout [15:0] DRAM_DQ, 14 output [1:0] DRAM_DQM, 15 output DRAM_RAS_N, 16 output DRAM_WE_N, 17 18 output I2C_SCLK, 19 inout I2C_SDAT, 20 21 inout [12:0] GPIO_2, 22 input [2:0] GPIO_2_IN, 23 24 inout [11:0] GPIO_A 25 ); 26 27 wire clk, reset; 28 wire [31:0] romaddr, romdata, ramaddr, ramrdata, ramwdata; 29 wire [31:0] uartrdata; 30 wire [31:0] cpurdata; 31 wire ramwe; 32 wire cs0,cs1; 33 34 assign cs0 = (ramaddr[31:16] == 16'h0000); 35 assign cs1 = (ramaddr[31:16] == 16'hE000); 36 assign clk = CLOCK_50; 37 38 assign reset = ~KEY[0]; 39 40 cpu32 cpu( 41 .clk(clk), 42 .reset(reset), 43 .i_addr(romaddr), 44 .i_data(romdata), 45 .d_data_r(cpurdata), 46 .d_data_w(ramwdata), 47 .d_addr(ramaddr), 48 .d_data_we(ramwe) 49 ); 50 51 // ugly hack for now 52 mux2 #(32) rdatamux( 53 .sel(cs1), 54 .in0(ramrdata), 55 .in1({24'b0,uartrdata}), 56 .out(cpurdata) 57 ); 58 59 rom rom( 60 .addr(romaddr[9:2]), 61 .data(romdata) 62 ); 63 64 ram #(32,8) ram( 65 .clk(clk), 66 .addr(ramaddr[9:2]), 67 .rdata(ramrdata), 68 .wdata(ramwdata), 69 .we(ramwe) 70 ); 71 72 uart uart0( 73 .clk(clk), 74 .reset(reset), 75 .we(cs1 & ramwe), 76 .wdata(ramwdata), 77 .rdata(uartrdata[7:0]), 78 .tx(GPIO_A[7]) 79 ); 80 81 assign GPIO_A[3] = uartrdata[0]; 82 83 reg [7:0] DBG; 84 assign LED = DBG; 85 86 always @(posedge clk) 87 if (ramwe && (ramaddr == 32'hF0000000)) 88 DBG <= ramwdata[7:0]; 89 90 endmodule 91 92 module rom( 93 input [7:0] addr, 94 output [31:0] data 95 ); 96 reg [31:0] rom[0:2**7]; 97 initial $readmemh("fw.txt", rom); 98 assign data = rom[addr]; 99 endmodule 100