de0board.v (2958B)
1 // Copyright 2012, Brian Swetland 2 3 module de0board( 4 input CLOCK_50, 5 output [9:0] LEDG, 6 output [6:0] HEX0_D, 7 output [6:0] HEX1_D, 8 output [6:0] HEX2_D, 9 output [6:0] HEX3_D, 10 output HEX0_DP, 11 output HEX1_DP, 12 output HEX2_DP, 13 output HEX3_DP, 14 output [3:0] VGA_R, 15 output [3:0] VGA_G, 16 output [3:0] VGA_B, 17 output VGA_HS, 18 output VGA_VS 19 ); 20 21 wire [15:0] status; 22 reg [31:0] count; 23 24 assign LEDG = 10'b1111111111; 25 assign HEX0_DP = 1'b1; 26 assign HEX1_DP = 1'b1; 27 assign HEX2_DP = 1'b1; 28 assign HEX3_DP = 1'b1; 29 30 hex2seven hex0(.in(status[3:0]),.out(HEX0_D)); 31 hex2seven hex1(.in(status[7:4]),.out(HEX1_D)); 32 hex2seven hex2(.in(status[11:8]),.out(HEX2_D)); 33 hex2seven hex3(.in(status[15:12]),.out(HEX3_D)); 34 35 wire clk; 36 assign clk = CLOCK_50; 37 38 reg clk25; 39 40 always @(posedge clk) 41 clk25 = ~clk25; 42 43 wire newline, advance; 44 wire [11:0] pixel; 45 wire [10:0] vram_addr; 46 wire [7:0] vram_data; 47 wire [7:0] line; 48 49 vga vga( 50 .clk(clk25), 51 .reset(1'b0), 52 .newline(newline), 53 .advance(advance), 54 .line(line), 55 .pixel(pixel), 56 .r(VGA_R), 57 .b(VGA_B), 58 .g(VGA_G), 59 .hs(VGA_HS), 60 .vs(VGA_VS) 61 ); 62 63 pixeldata pxd( 64 .clk(clk25), 65 .newline(newline), 66 .advance(advance), 67 .line(line), 68 .pixel(pixel), 69 .vram_data(vram_data), 70 .vram_addr(vram_addr) 71 ); 72 73 //assign status = 16'h1234; 74 75 wire [7:0] wdata; 76 reg [10:0] waddr; 77 wire we; 78 79 videoram #(8,11) vram( 80 .clk(clk), 81 .we(we), 82 .rdata(vram_data), 83 .raddr(vram_addr), 84 .wdata(wdata), 85 .waddr(waddr) 86 ); 87 88 wire [3:0] iir; 89 wire tdi, tdo, tck, cdr, sdr, udr, uir; 90 reg [15:0] dr; 91 reg [3:0] ir; 92 93 jtag jtag0( 94 .tdi(tdi), 95 .tdo(tdo), 96 .tck(tck), 97 .ir_in(iir), 98 .virtual_state_cdr(cdr), 99 .virtual_state_sdr(sdr), 100 .virtual_state_udr(udr), 101 .virtual_state_uir(uir) 102 ); 103 104 parameter IR_ADDR = 4'h1; 105 parameter IR_DATA = 4'h2; 106 107 always @(posedge tck) begin 108 if (uir) 109 ir <= iir; 110 if (cdr) 111 dr <= 16'hABCD; 112 if (sdr) 113 dr <= { tdi, dr[15:1] }; 114 end 115 assign tdo = dr[0]; 116 117 wire update; 118 119 sync sync0( 120 .in(udr), 121 .clk_in(tck), 122 .out(update), 123 .clk_out(clk) 124 ); 125 126 assign wdata = dr[7:0]; 127 assign we = update & (ir == IR_DATA); 128 129 always @(posedge clk) 130 if (update) case (iir) 131 IR_ADDR: waddr <= dr[10:0]; 132 IR_DATA: waddr <= waddr + 11'd1; 133 endcase 134 135 reg [31:0] dispreg; 136 assign status = dispreg[15:0]; 137 138 endmodule 139 140 module sync( 141 input clk_in, 142 input clk_out, 143 input in, 144 output out 145 ); 146 reg toggle; 147 reg [2:0] sync; 148 always @(posedge clk_in) 149 if (in) toggle <= ~toggle; 150 always @(posedge clk_out) 151 sync <= { sync[1:0], toggle }; 152 assign out = (sync[2] ^ sync[1]); 153 endmodule 154 155 156 module hex2seven( 157 input [3:0] in, 158 output reg [6:0] out 159 ); 160 161 always @(*) case (in) 162 4'h0: out = 7'b1000000; 163 4'h1: out = 7'b1111001; 164 4'h2: out = 7'b0100100; 165 4'h3: out = 7'b0110000; 166 4'h4: out = 7'b0011001; 167 4'h5: out = 7'b0010010; 168 4'h6: out = 7'b0000011; 169 4'h7: out = 7'b1111000; 170 4'h8: out = 7'b0000000; 171 4'h9: out = 7'b0011000; 172 4'hA: out = 7'b0001000; 173 4'hB: out = 7'b0000011; 174 4'hC: out = 7'b1000110; 175 4'hD: out = 7'b0100001; 176 4'hE: out = 7'b0000110; 177 4'hF: out = 7'b0001110; 178 endcase 179 180 endmodule 181