isa.txt (1961B)
1 CPU32 Instruction Set Architecture 2 ---------------------------------- 3 4 Encoding Formats 5 ---------------- 6 7 R OOOOFFFFAAAABBBBDDDDXXXXXXXXXXXX register 8 I OOOOFFFFAAAADDDDIIIIIIIIIIIIIIII immediate 9 10 Core Instruction Set 11 -------------------- 12 13 0X ALU Rd, Ra, Rb see ALU ops below 14 1X ALU Rd, Ra, #I 15 16 22 LW Rd, [Ra, #I] Rd = M(Ra + I) 17 32 SW Rd, [Ra, #I] M(Ra + I) = Rd 18 19 4F BLZ Rd, Ra, rel if (Ra == 0) { Rd = PC + 4, PC += I } 20 5F BLNZ Rd, Ra, rel if (Ra != 0) { Rd = PC + 4, PC += I } 21 6F BLZ Rd, Ra, Rb if (Ra == 0) { Rd = PC + 4, PC = Rb } 22 7F BLNZ Rd, Ra, Rb if (Ra != 0) { Rd = PC + 4, PC = Rb } 23 24 82 LW Rd, [PC, #I] Rd = M(PC + 8 + I) 25 26 ALU Instructions (replace Rb w/ #I for immediate form) 27 ------------------------------------------------------ 28 29 X0 OR Rd, Ra, Rb Rd = Ra | Rb 30 X1 AND Rd, Ra, Rb Rd = Ra & Rb 31 X2 ADD Rd, Ra, Rb Rd = Ra + Rb 32 X3 SUB Rd, Ra, Rb Rd = Ra - Rb 33 X4 SHL Rd, Ra, Rb Rd = Ra << Rb[0:4] 34 X5 SHR Rd, Ra, Rb Rd = Ra >> Rb[0:4] 35 X6 XOR Rd, Ra, Rb Rd = Ra ^ Rb 36 X7 TBS Rd, Ra, Rb Rd = Ra & (1 << Rb) 37 38 X8 BIS Rd, Ra, Rb Rd = Ra | (1 << Rb) 39 X9 BIC Rd, Ra, Rb Rd = Ra & ~(1 << Rb) 40 XA SLT Rd, Ra, Rb Rd = Ra < Rb 41 XB SGT Rd, Ra, Rb Rd = Ra > Rb 42 XC MLO Rd, Ra, Rb Rd = (Ra & 0xFFFF0000) | (Rb & 0xFFFF) 43 XD MHI Rd, Ra, Rb Rd = (Ra & 0xFFFF) | (Rb << 16) 44 XE ASR Rd, Ra, Rb Rd = (Ra >>> Rb[0:4]) 45 XF NOP Rd, Ra, Rb Rd = Ra 46 47 Pseudo Instructions 48 ------------------- 49 50 MOV Rd, Rb OR Rd, R0, Rb 51 SNE Rd, Ra, Rb SUB Rd, Ra, Rb 52 NOT Rd, Ra XOR Rd, Ra, #-1 53 NOP BLNZ Rz, Rz, 0xFFFF (0x5FFFFFFF) 54 55 Registers 56 --------- 57 R0-R3 args / results 58 R13 stack pointer (aka SP) 59 R14 link (aka LR) 60 R15 zero (aka ZR) 61 62 Open Issues 63 ----------- 64 - syntax for conditional branches is confusing 65 - consider allowing B [Rx] as well as B Rx? 66 - allow # in front of constants