alu.v (878B)
1 // CPU32 ALU 2 // 3 // Copyright 2012, Brian Swetland. Use at your own risk. 4 5 `timescale 1ns/1ns 6 7 module alu ( 8 input [3:0] opcode, 9 input [31:0] left, 10 input [31:0] right, 11 output reg [31:0] out 12 ); 13 14 wire [31:0] rbit; 15 assign rbit = (1 << right[4:0]); 16 17 always @ (*) 18 case (opcode) 19 4'b0000: out <= (left | right); 20 4'b0001: out <= (left & right); 21 4'b0010: out <= (left + right); 22 4'b0011: out <= (left - right); 23 4'b0100: out <= (left << right[4:0]); 24 4'b0101: out <= (left >> right[4:0]); 25 4'b0110: out <= (left ^ right); 26 4'b0111: out <= (left & rbit); 27 4'b1000: out <= (left | rbit); 28 4'b1001: out <= (left & ~rbit); 29 4'b1010: out <= (left < right) ? 1 : 0; 30 4'b1011: out <= (left > right) ? 1 : 0; 31 4'b1100: out <= { left[31:16], right[15:0] }; 32 4'b1101: out <= { right[15:0], left[31:16] }; 33 4'b1110: out <= (left >>> right[4:0]); 34 4'b1111: out <= left; 35 endcase 36 endmodule