chardata.v (2609B)
1 // Copyright 2012, Brian Swetland 2 // 3 // Pixel Data Reader / Character Data Reader 4 // 5 // assert newline and provide line address to start linefetch 6 // character data will be provided on cdata two clocks later 7 // 8 // assert next to advance: character data will be provided two clocks later 9 // 10 // vram_addr/vram_data: connect to sync sram 11 12 `timescale 1ns/1ns 13 14 module pixeldata( 15 input clk, 16 input newline, 17 input advance, 18 input [7:0] line, 19 20 output reg [11:0] pixel, 21 22 input [7:0] vram_data, 23 output [10:0] vram_addr 24 ); 25 26 wire [7:0] new_cdata; 27 reg next; 28 29 chardata chardata( 30 .clk(clk), 31 .newline(newline), 32 .line(line), 33 .next(next), 34 .cdata(new_cdata), 35 .vram_data(vram_data), 36 .vram_addr(vram_addr) 37 ); 38 39 reg [7:0] cdata, next_cdata; 40 reg [3:0] bitcount, next_bitcount; 41 reg [1:0] state, next_state; 42 43 always @(*) begin 44 next_bitcount = bitcount; 45 next_cdata = cdata; 46 next = 1'b0; 47 48 /* s0 machine is used to wait until the first cdata 49 * is ready after a newline signal, load that cdata, 50 * then enter the shift-out (s0=0) mode 51 */ 52 case (state) 53 2'h3: next_state = 2'h2; 54 2'h2: next_state = 2'h1; 55 2'h1: begin 56 next_state = 2'h0; 57 next_cdata = new_cdata; 58 end 59 2'h0: begin 60 next_state = 2'h0; 61 if (advance) 62 next_bitcount = bitcount - 4'd1; 63 if (bitcount == 4'h4) 64 next = 1'b1; 65 if (bitcount == 4'h0) 66 next_cdata = new_cdata; 67 end 68 endcase 69 70 if (newline) begin 71 next_state = 2'h3; 72 next_bitcount = 4'hF; 73 end 74 75 pixel = (cdata[bitcount[3:1]] ? 12'hFFF : 12'h00F); 76 end 77 78 always @(posedge clk) begin 79 bitcount <= next_bitcount; 80 state <= next_state; 81 cdata <= next_cdata; 82 end 83 84 endmodule 85 86 87 module chardata( 88 input clk, 89 input newline, 90 input next, 91 input [7:0] line, 92 output reg [7:0] cdata, 93 94 input [7:0] vram_data, 95 output reg [10:0] vram_addr 96 ); 97 98 `define SWAIT 2'h0 99 `define SLOAD 2'h1 100 `define SLATCH 2'h2 101 102 reg [7:0] pattern_rom [0:1023]; 103 reg [2:0] pline, next_pline; 104 105 reg [1:0] state, next_state; 106 reg [10:0] next_addr; 107 reg [7:0] next_cdata; 108 109 initial $readmemh("prom.txt", pattern_rom); 110 111 always @(*) begin 112 next_state = state; 113 next_addr = vram_addr; 114 next_cdata = cdata; 115 next_pline = pline; 116 if (newline) begin 117 next_state = `SLOAD; 118 next_addr = { line[7:3], 6'b0 }; 119 next_pline = line[2:0]; 120 end 121 case (state) 122 `SWAIT: if (next) begin 123 next_state = `SLOAD; 124 end 125 `SLOAD: begin 126 next_state = `SLATCH; 127 end 128 `SLATCH: begin 129 next_state = `SWAIT; 130 next_addr = vram_addr + 11'd1; 131 next_cdata = pattern_rom[{vram_data, pline}]; 132 end 133 endcase 134 end 135 136 always @(posedge clk) begin 137 state <= next_state; 138 vram_addr <= next_addr; 139 cdata <= next_cdata; 140 pline <= next_pline; 141 end 142 143 endmodule