cpu32

verilog 32bit cpu experiment
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control.v (1532B)


      1 // Copyright 2012, Brian Swetland.  Use at your own risk.
      2 
      3 `timescale 1ns/1ns
      4 module control (
      5 	input [3:0] opcode,
      6 	input [3:0] opfunc,
      7 	input ctl_adata_zero,		// 1=(adata==0)
      8 	input hazard,
      9 
     10 	output ctl_alu_pc,		// 0=adata, 1=pc+4 -> alu.left
     11 	output ctl_alu_imm,		// 0=bdata, 1=signed_imm16
     12 	output ctl_regs_we,		// 1=write to reg file
     13 	output ctl_ram_we,		// 1=write to ram
     14 	output ctl_alu_altdest,		// 0=alu.daddr=opd, 1=alu.daddr=opb
     15 	output ctl_wdata_ram,		// 0=alu, 1=ram
     16 
     17 	output ctl_branch_ind,	// 0=relative branch, 1=indirect branch
     18 	output ctl_branch_taken	// 0=pc=pc+4, 1=pc=branch_to
     19 	);
     20 
     21 wire ctl_branch_op;
     22 wire ctl_branch_nz;
     23 
     24 reg [6:0] control;
     25 
     26 always @ (*) begin
     27 	case (opcode)
     28 	4'b0000: control = 7'b0010000; // ALU Rd, Ra, Rb
     29 	4'b0001: control = 7'b0110100; // ALU Rd, Ra, #I
     30 	4'b0010: control = 7'b0110101; // LW Rd, [Ra, #I]
     31 	4'b0011: control = 7'b0101000; // SW Rd, [Ra, #I]
     32 	4'b0100: control = 7'b1010110; // BLZ rel16
     33 	4'b0101: control = 7'b1010110; // BLNZ rel16
     34 	4'b0110: control = 7'b1010010; // BLZ Rb
     35 	4'b0111: control = 7'b1010010; // BLNZ Rb
     36 	4'b1000: control = 7'b1110101; // LW Rd, [PC, #I]
     37 	4'b1110: control = 7'b1100000; // NOP
     38 	default: control = 7'b0000000;
     39 	endcase
     40 
     41 	if (hazard) control = 7'b1100000;
     42 end
     43 
     44 assign {
     45 	ctl_alu_pc, ctl_alu_imm, ctl_regs_we, ctl_ram_we, 
     46 	ctl_alu_altdest, ctl_branch_op, ctl_wdata_ram
     47 	} = control;
     48 
     49 assign ctl_branch_nz = opcode[0];
     50 assign ctl_branch_ind = opcode[1];
     51 assign ctl_branch_taken = (ctl_branch_op & (ctl_adata_zero != ctl_branch_nz));
     52 
     53 endmodule
     54