dualsyncram.v (643B)
1 // Copyright 2012, Brian Swetland 2 3 `timescale 1ns/1ns 4 5 module dualsyncram #(parameter DWIDTH=16, parameter AWIDTH=8) ( 6 input clk, 7 input [AWIDTH-1:0] a_addr, 8 input [DWIDTH-1:0] a_wdata, 9 input a_we, 10 input [AWIDTH-1:0] b_addr, 11 input [DWIDTH-1:0] b_wdata, 12 input b_we, 13 //input [AWIDTH-1:0] a_raddr, 14 output reg [DWIDTH-1:0] a_rdata, 15 //input [AWIDTH-1:0] b_raddr, 16 output reg [DWIDTH-1:0] b_rdata 17 ); 18 19 reg [DWIDTH-1:0] mem[0:2**AWIDTH-1]; 20 21 always @(posedge clk) begin 22 if (a_we) 23 mem[a_addr] <= a_wdata; 24 a_rdata <= mem[a_addr]; 25 end 26 27 always @(posedge clk) begin 28 if (b_we) 29 mem[b_addr] <= b_wdata; 30 b_rdata <= mem[b_addr]; 31 end 32 33 endmodule