library.v (2806B)
1 // Useful tidbits 2 // 3 // Copyright 2009, Brian Swetland. Use at your own risk. 4 5 `timescale 1ns/1ns 6 7 module decoder2 ( 8 input [1:0] in, 9 output out0, out1, out2, out3 10 ); 11 12 reg [3:0] out; 13 14 assign out0 = out[0]; 15 assign out1 = out[1]; 16 assign out2 = out[2]; 17 assign out3 = out[3]; 18 19 always @ (*) 20 case (in) 21 2'b00: out = 4'b0001; 22 2'b01: out = 4'b0010; 23 2'b10: out = 4'b0100; 24 2'b11: out = 4'b1000; 25 endcase 26 endmodule 27 28 29 module decoder8 ( 30 input [2:0] in, 31 output reg [7:0] out 32 ); 33 34 always @ (*) 35 case (in) 36 3'b000: out = 8'b00000001; 37 3'b001: out = 8'b00000010; 38 3'b010: out = 8'b00000100; 39 3'b011: out = 8'b00001000; 40 3'b100: out = 8'b00010000; 41 3'b101: out = 8'b00100000; 42 3'b110: out = 8'b01000000; 43 3'b111: out = 8'b10000000; 44 endcase 45 endmodule 46 47 module decoder8en (input [2:0] in, input en, output reg [7:0] out); 48 always @ (*) 49 if (en) 50 case (in) 51 3'b000: out = 8'b00000001; 52 3'b001: out = 8'b00000010; 53 3'b010: out = 8'b00000100; 54 3'b011: out = 8'b00001000; 55 3'b100: out = 8'b00010000; 56 3'b101: out = 8'b00100000; 57 3'b110: out = 8'b01000000; 58 3'b111: out = 8'b10000000; 59 endcase 60 else 61 out = 8'b00000000; 62 endmodule 63 64 65 module mux2 #(parameter WIDTH=16) ( 66 input sel, 67 input [WIDTH-1:0] in0, in1, 68 output [WIDTH-1:0] out 69 ); 70 71 assign out = sel ? in1 : in0 ; 72 endmodule 73 74 75 module mux4 #(parameter WIDTH=16) ( 76 input [1:0] sel, 77 input [WIDTH-1:0] in0,in1,in2,in3, 78 output reg [WIDTH-1:0] out 79 ); 80 always @ (*) 81 case (sel) 82 2'b00: out <= in0; 83 2'b01: out <= in1; 84 2'b10: out <= in2; 85 2'b11: out <= in3; 86 endcase 87 endmodule 88 89 90 module mux8 #(parameter WIDTH=16) ( 91 input [2:0] sel, 92 input [WIDTH-1:0] in0,in1,in2,in3,in4,in5,in6,in7, 93 output reg [WIDTH-1:0] out 94 ); 95 always @ (*) 96 case (sel) 97 3'b000: out <= in0; 98 3'b001: out <= in1; 99 3'b010: out <= in2; 100 3'b011: out <= in3; 101 3'b100: out <= in4; 102 3'b101: out <= in5; 103 3'b110: out <= in6; 104 3'b111: out <= in7; 105 endcase 106 endmodule 107 108 109 module mux16 #(parameter WIDTH=16) ( 110 input [3:0] sel, 111 input [WIDTH-1:0] in00,in01,in02,in03,in04,in05,in06,in07, 112 input [WIDTH-1:0] in08,in09,in10,in11,in12,in13,in14,in15, 113 output reg [WIDTH-1:0] out 114 ); 115 always @ (*) 116 case (sel) 117 4'b0000: out <= in00; 118 4'b0001: out <= in01; 119 4'b0010: out <= in02; 120 4'b0011: out <= in03; 121 4'b0100: out <= in04; 122 4'b0101: out <= in05; 123 4'b0110: out <= in06; 124 4'b0111: out <= in07; 125 4'b1000: out <= in08; 126 4'b1001: out <= in09; 127 4'b1010: out <= in10; 128 4'b1011: out <= in11; 129 4'b1100: out <= in12; 130 4'b1101: out <= in13; 131 4'b1110: out <= in14; 132 4'b1111: out <= in15; 133 endcase 134 endmodule 135 136 137 module register #(parameter WIDTH=16) ( 138 input clk, 139 input en, 140 input reset, 141 input [WIDTH-1:0] din, 142 output [WIDTH-1:0] dout 143 ); 144 145 reg [WIDTH-1:0] data; 146 initial data = 0; 147 always @ (posedge clk or posedge reset) 148 if (reset) 149 data <= 32'h00000000; 150 else if (en) 151 data <= din; 152 153 assign dout = data; 154 endmodule 155