ram.v (428B)
1 // RAM - Does not instantiate optimally on Altera FPGAs 2 // 3 // Copyright 2009, Brian Swetland. Use at your own risk. 4 5 `timescale 1ns/1ns 6 7 module ram #(parameter DWIDTH=16, parameter AWIDTH=3) ( 8 input clk, input we, 9 input [AWIDTH-1:0] addr, 10 input [DWIDTH-1:0] wdata, 11 output [DWIDTH-1:0] rdata 12 ); 13 14 reg [DWIDTH-1:0] R[0:2**AWIDTH-1]; 15 16 always @ (posedge clk) 17 if (we) 18 R[addr] <= wdata; 19 20 assign rdata = R[addr]; 21 22 endmodule