cpu32

verilog 32bit cpu experiment
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regfile.v (548B)


      1 // Dual-reader / Single-writer Register File
      2 //
      3 // Copyright 2009, Brian Swetland.  Use at your own risk.
      4 
      5 `timescale 1ns/1ns
      6 
      7 module regfile (
      8 	input reset,
      9 	input clk, input we,
     10 	input [3:0] wsel, input [31:0] wdata,
     11 	input [3:0] asel, output [31:0] adata,
     12 	input [3:0] bsel, output [31:0] bdata
     13 	);
     14 
     15 reg [31:0] R[0:15];
     16 
     17 initial
     18 	R[4'b1111] = 32'b0;
     19 
     20 always @ (posedge clk) begin
     21 	if (we)
     22 		case(wsel)
     23 		4'b1111: ;
     24 		default: R[wsel] <= wdata;
     25 		endcase
     26 //	R[4'b1111] <= 32'b0;
     27 end
     28 
     29 assign adata = R[asel];
     30 assign bdata = R[bsel];
     31    
     32 endmodule