testbench.v (1783B)
1 // CPU32 Test Bench - For testing in iverilog. 2 // 3 // Copyright 2012, Brian Swetland. Use at your own risk. 4 5 `timescale 1ns/1ns 6 7 module testbench; 8 9 reg clk, reset; 10 wire [31:0] romaddr, romdata, ramaddr, ramrdata, ramwdata; 11 wire ramwe; 12 13 initial begin 14 clk = 0; 15 reset = 0; 16 #1 reset = 1; 17 #19 reset = 0; 18 end 19 20 always 21 #10 clk = ~clk; 22 23 wire [7:0] urdata; 24 25 cpu32 cpu( 26 .clk(clk), 27 .reset(reset), 28 .i_addr(romaddr), 29 .i_data(romdata), 30 .d_data_r(ramrdata), 31 // .d_data_r({24'b0,urdata}), 32 .d_data_w(ramwdata), 33 .d_addr(ramaddr), 34 .d_data_we(ramwe) 35 ); 36 37 dualsyncram #(32,12) memory( 38 .clk(clk), 39 .a_addr(romaddr[13:2]), 40 .a_rdata(romdata), 41 .a_wdata(32'b0), 42 .a_we(1'b0), 43 .b_addr(ramaddr[13:2]), 44 .b_rdata(ramrdata), 45 .b_wdata(ramwdata), 46 .b_we(ramwe) 47 ); 48 49 initial $readmemh("test.hex",memory.mem); 50 51 /* 52 wire tx; 53 uart uart0( 54 .clk(clk), 55 .reset(reset), 56 .wdata(ramwdata[7:0]), 57 .rdata(urdata), 58 .we(ramwe & (ramaddr[31:28] == 4'hE)), 59 .tx(tx) 60 ); 61 */ 62 63 teleprinter io( 64 .clk(clk), 65 .we(ramwe), 66 .cs(ramaddr[31:28] == 4'hE), 67 .data(ramwdata[7:0]) 68 ); 69 70 initial begin 71 $dumpfile("testbench.vcd"); 72 $dumpvars(0,testbench); 73 end 74 75 initial #1000 $finish; 76 77 78 always @(posedge clk) begin 79 if (cpu.ir == 32'hFFFFFFFF) begin 80 $display("PC> EXIT"); 81 $finish(); 82 end 83 if (cpu.ir == 32'hFFFFFFFE) begin 84 $display("PC> ERROR"); 85 $finish(); 86 end 87 if (cpu.hazard_rrw) 88 $display("PC> %h I> HAZARD", cpu.pc); 89 else if (!reset) 90 $display("PC> %h I> %h R> %h %h %h %h %h %h %h %h", 91 cpu.pc, cpu.ir, 92 cpu.REGS.R[0], 93 cpu.REGS.R[1], 94 cpu.REGS.R[2], 95 cpu.REGS.R[3], 96 cpu.REGS.R[11], 97 cpu.REGS.R[12], 98 cpu.REGS.R[13], 99 cpu.REGS.R[14] 100 ); 101 end 102 103 endmodule 104 105 module teleprinter ( 106 input we, 107 input cs, 108 input clk, 109 input [7:0] data 110 ); 111 always @(posedge clk) 112 if (cs & we) 113 $write("%c", data); 114 endmodule 115