cpu32

verilog 32bit cpu experiment
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uart.v (1648B)


      1 // Copyright 2012, Brian Swetland.  If it breaks, you keep both halves.
      2 
      3 // todo: wire up a divisor register
      4 
      5 `timescale 1ns/1ns
      6 
      7 module uart(
      8 	input clk,
      9 	input reset,
     10 	input [7:0] wdata,
     11 	output [7:0] rdata,
     12 	input we,
     13 	output tx
     14 	);
     15 
     16 reg out;
     17 reg busy;
     18 reg [7:0] data;
     19 reg [3:0] state;
     20 wire next_bit;
     21 
     22 counter bitcounter(
     23 	.clk(clk),
     24 	.reset(reset),
     25 	.max(16'd434),
     26 	.overflow(next_bit)
     27 	);
     28 
     29 assign tx = out;
     30 assign rdata = { 7'b0, busy };
     31 
     32 always @(posedge clk or posedge reset)
     33 begin
     34 	if (reset) begin
     35 		out <= 1'b1;
     36 		busy <= 1'b1;
     37 		state <= 4'b0010;
     38 		data <= 8'hFF;
     39 	end else begin
     40 		if (we) begin
     41 			data <= wdata;
     42 			busy <= 1'b1;
     43 		end
     44 		if (next_bit) begin
     45 			case (state)
     46 			4'b0000: begin state <= (busy ? 4'b0001 : 4'b0000); out <= 1'b1; end
     47 			4'b0001: begin state <= 4'b0010; out <= 1'b0; end
     48 			4'b0010: begin state <= 4'b0011; out <= data[0]; end
     49 			4'b0011: begin state <= 4'b0100; out <= data[1]; end
     50 			4'b0100: begin state <= 4'b0101; out <= data[2]; end
     51 			4'b0101: begin state <= 4'b0110; out <= data[3]; end
     52 			4'b0110: begin state <= 4'b0111; out <= data[4]; end
     53 			4'b0111: begin state <= 4'b1000; out <= data[5]; end
     54 			4'b1000: begin state <= 4'b1001; out <= data[6]; end
     55 			4'b1001: begin state <= 4'b1010; out <= data[7]; end
     56 			4'b1010: begin state <= 4'b0000; out <= 1'b1; busy <= 1'b0; end
     57 			endcase
     58 		end
     59 	end
     60 end
     61 
     62 endmodule
     63 
     64 module counter(
     65 	input clk,
     66 	input reset,
     67 	input [15:0] max,
     68 	output overflow 
     69 	);
     70 
     71 reg [15:0] count;
     72 
     73 assign overflow = (count == max);
     74 
     75 always @(posedge clk or posedge reset)
     76 begin
     77 	if (reset) 
     78 		count <= 16'b0;
     79 	else
     80 		count <= overflow ? 16'b0 : (count + 16'b1);
     81 end
     82 
     83 endmodule
     84 
     85