cpu32

verilog 32bit cpu experiment
git clone http://frotz.net/git/cpu32.git
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uart_tb.v (434B)

      1 // Copyright 2012, Brian Swetland.  If it breaks, you keep both halves.
      2 
      3 `timescale 1ns/1ns
      4 
      5 module uart_tb ();
      6 
      7 reg clk;
      8 reg reset;
      9 
     10 uart uart0(
     11 	.wdata("A"),
     12 	.we(1),
     13 	.reset(reset),
     14 	.clk(clk),
     15 	.bdiv(434)
     16 	);
     17 
     18 initial begin
     19 	reset = 1;
     20 	#30 ;
     21 	reset = 0;
     22 end
     23 
     24 always begin
     25 	clk = 0;
     26 	#10 ;
     27 	clk = 1;
     28 	#10 ;
     29 end
     30 
     31 initial #1000000 $finish;
     32 
     33 initial begin
     34         $dumpfile("uart.vcd");
     35         $dumpvars(0,uart_tb);
     36 end
     37 
     38 endmodule
     39