vga.v (1675B)
1 // Copyright 2012, Brian Swetland 2 3 `timescale 1ns/1ns 4 5 // Vert: 2xSync 30xBack 480xData 12xFront -> 524 lines 6 // Horz: 96xSync 48xBack 640xData 16xFront -> 800 pixels 7 // 8 // CLK: 25MHz, px=40nS, line=32uS, frame=16.768mS 9 10 module vga( 11 input clk, 12 input reset, 13 output reg hs, 14 output reg vs, 15 output reg [3:0] r, 16 output reg [3:0] g, 17 output reg [3:0] b, 18 19 output reg newline, 20 output reg advance, 21 output reg [7:0] line, 22 input [11:0] pixel 23 ); 24 25 reg [9:0] hcount; 26 reg [9:0] vcount; 27 28 reg [9:0] next_hcount; 29 reg [9:0] next_vcount; 30 reg next_hs, next_vs; 31 reg active; 32 reg next_startline; 33 reg [9:0] next_line; 34 35 always @* begin 36 if (hcount == 10'd799) begin 37 if (vcount == 10'd523) 38 next_vcount = 10'd0; 39 else 40 next_vcount = vcount + 10'd1; 41 next_hcount = 10'd0; 42 end else begin 43 next_vcount = vcount; 44 next_hcount = hcount + 10'd1; 45 end 46 47 if (reset) begin 48 next_hcount = 10'd0; 49 next_vcount = 10'd0; 50 end 51 52 if (next_hcount == 0) 53 next_startline = 1'b1; 54 else 55 next_startline = 1'b0; 56 57 if (next_hcount < 10'd96) 58 next_hs = 1'b0; 59 else 60 next_hs = 1'b1; 61 62 if (next_vcount < 10'd2) 63 next_vs = 1'b0; 64 else 65 next_vs = 1'b1; 66 67 active = 1'b0; 68 if ((next_vcount > 31) && (next_vcount < 512)) 69 if ((next_hcount > 143) && (next_hcount < 784)) 70 active = 1'b1; 71 72 next_line = next_vcount - 10'd32; 73 end 74 75 always @(posedge clk) begin 76 hcount <= next_hcount; 77 vcount <= next_vcount; 78 hs <= next_hs; 79 vs <= next_vs; 80 81 /* signals to pixel generator */ 82 newline <= next_startline; 83 advance <= active; 84 line <= next_line[8:1]; 85 86 if (active) begin 87 r <= pixel[11:8]; 88 g <= pixel[7:4]; 89 b <= pixel[3:0]; 90 end else begin 91 r <= 4'd0; 92 g <= 4'd0; 93 b <= 4'd0; 94 end 95 end 96 97 endmodule