cpu32

verilog 32bit cpu experiment
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videoram.v (507B)


      1 // Copyright 2012, Brian Swetland.  Use at your own risk.
      2 //
      3 // sync sram with independent read/write addressing
      4 
      5 `timescale 1ns/1ns
      6 
      7 module videoram #(parameter DWIDTH=16, parameter AWIDTH=8) (
      8 	input clk, input we,
      9 	input [AWIDTH-1:0] waddr,
     10 	input [DWIDTH-1:0] wdata,
     11 	input [AWIDTH-1:0] raddr,
     12 	output reg [DWIDTH-1:0] rdata
     13 	);
     14 
     15 reg [DWIDTH-1:0] mem[0:2**AWIDTH-1];
     16 
     17 initial $readmemh("vram.txt", mem);
     18 
     19 always @ (posedge clk) begin
     20 	if (we)
     21 		mem[waddr] <= wdata;
     22 	rdata <= mem[raddr];
     23 end
     24 
     25 endmodule