jtag-mpsse

JTAG tools for FTDI MPSSE transports
git clone http://frotz.net/git/jtag-mpsse.git
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zynq.h (2203B)


      1 
      2 /* ARM DAP Controller (4bit IR) */
      3 #define DAP_IR_SIZE		4
      4 
      5 #define DAP_IR_ABORT		0x08
      6 #define DAP_IR_DPACC		0x0A
      7 #define DAP_IR_APACC		0x0B
      8 #define DAP_IR_IDCODE		0x0E
      9 #define DAP_IR_BYPASS		0x0F
     10 
     11 #define XPACC_STATUS(n)		((n) & 0x3)
     12 #define XPACC_WAIT		0x1
     13 #define XPACC_OK		0x2
     14 #define XPACC_RD(n)		(0x1 | (((n) >> 1) & 6))
     15 #define XPACC_WR(n)		(0x0 | (((n) >> 1) & 6))
     16 
     17 #define DPACC_RESERVED		0x0
     18 #define DPACC_CSW		0x4
     19 #define DPACC_SELECT		0x8
     20 #define DPACC_RDBUFF		0xC
     21 
     22 #define DPCSW_CSYSPWRUPACK	(1 << 31)
     23 #define DPCSW_CSYSPWRUPREQ	(1 << 30)
     24 #define DPCSW_CDBGPWRUPACK	(1 << 29)
     25 #define DPCSW_CDBGPWRUPREQ	(1 << 28)
     26 #define DPCSW_CDBGRSTACK	(1 << 27)
     27 #define DPCSW_CDBGRSTREQ	(1 << 26)
     28 #define DPCSW_TRNCNT(n)		(((n) & 0x3FF) << 12)
     29 #define DPCSW_MASKLANE(n)	(((n) & 0xF) << 8) // pushed verify or compare
     30 #define DPCSW_WDATAERR		(1 << 7) // reserved on jtag
     31 #define DPCSW_READOK		(1 << 6) // reserved on jtag
     32 #define DPCSW_STICKYERR		(1 << 5)
     33 #define DPCSW_STICKYCMP		(1 << 4)
     34 #define DPCSW_TRNMODE_NORMAL	(0 << 2)
     35 #define DPCSW_TRNMODE_PUSH_VRFY	(1 << 2)
     36 #define DPCSW_TRNMODE_PUSH_CMP	(2 << 2)
     37 #define DPCSW_STICKYORUN	(1 << 1)
     38 #define DPCSW_ORUNDETECT	(1 << 0)
     39 
     40 #define DPSEL_APSEL(n)		(((n) & 0xFF) << 24)
     41 #define DPSEL_APBANKSEL(a)	((a) & 0xF0)
     42 #define DPSEL_CTRLSEL		(1 << 0) // reserved on jtag
     43 
     44 /* Reading RDBUFF returns 0, has no side effects */
     45 /* Can be used to obtain final read result and ack values at end of seq */
     46 
     47 #define APACC_CSW		0x00
     48 #define APACC_TAR		0x04
     49 #define APACC_DRW		0x0C
     50 #define APACC_BD0		0x10
     51 #define APACC_BD1		0x14
     52 #define APACC_BD2		0x18
     53 #define APACC_BD3		0x1C
     54 #define APACC_CFG		0xF4
     55 #define APACC_BASE		0xF8
     56 #define APACC_IDR		0xFC
     57 
     58 
     59 /* Xilinx TAP Controller (6bit IR) */
     60 #define XIL_IR_SIZE		6
     61 
     62 #define XIL_EXTEST		0x00
     63 #define XIL_SAMPLE		0x01
     64 #define XIL_USER1		0x02
     65 #define XIL_USER2		0x03
     66 #define XIL_USER3		0x22
     67 #define XIL_USER4		0x23
     68 #define XIL_CFG_OUT		0x04
     69 #define XIL_CFG_IN		0x05
     70 #define XIL_USERCODE		0x08
     71 #define XIL_IDCODE		0x09
     72 #define XIL_ISC_ENABLE		0x10
     73 #define XIL_ISC_PROGRAM		0x11
     74 #define XIL_ISC_PROGRAM_SECURITY 0x12
     75 #define XIL_ISC_NOOP		0x14
     76 #define XIL_ISC_READ		0x1B
     77 #define XIL_ISC_DISABLE		0x17
     78 #define XIL_BYPASS		0x3F
     79