v7debug-registers.h (4516B)
1 2 #ifndef _V7DEBUG_REGISTERS_H_ 3 #define _V7DEBUG_REGISTERS_H_ 4 5 // ARM Debug Interface 6 7 // See: Cortex R5 r1p2 TRM 8 // http://infocenter.arm.com/help/topic/com.arm.doc.ddi0460d/DDI0460D_cortex_r5_r1p2_trm.pdf 9 10 #define DBGDIDR 0x000 // Debug ID Register 11 #define DBGWFAR 0x018 // Watchpoint Fault Address Register 12 #define DBGVCR 0x01C // Vector Catch Register 13 #define DBGECR 0x024 // ? 14 #define DBGDSCCR 0x028 // Debug State Cache Control Register 15 #define DBGDSMCR 0x02C // ? 16 #define DBGDTRRX 0x080 // Data Transfer Register (host->target) 17 #define DBGITR 0x084 // Instruction Transfer Register 18 #define DBGDSCR 0x088 // Debug Status and Control Register 19 #define DBGDTRTX 0x08C // Data Transfer Register (target->host) 20 #define DBGDRCR 0x090 // Debug Run Control Register 21 #define DBGPCSR 0x0A0 // ? 22 #define DBGCIDSR 0x0A4 // ? 23 #define DBGBVR 0x100 // Breakpoint Value Registers 24 #define DBGBCR 0x140 // Breakpoint Control Registers 25 #define DBGWVR 0x180 // Watchpoint Value Registers 26 #define DBGWCR 0x1C0 // Watchpoint Control Registers 27 #define DBGOSLAR 0x300 // ? 28 #define DBGOSLSR 0x304 // Operating System Lock Status Register 29 #define DBGOSSRR 0x308 // ? 30 #define DBGPRCR 0x310 // Device Power-Down and Reset Control Register 31 #define DBGPRSR 0x314 // Device Power-Down and Reset Status Register 32 #define DBGLAR 0xFB0 // Lock Access Register 33 #define DBGLSR 0xFB4 // Lock Status Register 34 #define DBGAUTHSTATUS 0xDB8 // Authentication Status Register 35 #define DBGDEVID 0xFC8 // Device ID 36 #define DBGDEVTYPE 0xFCC // Device Type 37 #define DBGPID0 0xFD0 38 #define DBGCID0 0xFF0 39 40 #define DSCR_RXFULL (1 << 30) // (cleared on read) 41 #define DSCR_TXFULL (1 << 29) // (cleared on read) 42 #define DSCR_PIPEADV (1 << 25) // (cleared on DRCR write) set on instr exec 43 #define DSCR_INSTRCOMPL (1 << 24) // 0 if cpu executing from ITR 44 #define DSCR_DCC_MASK (3 << 20) // DTR access mode 45 #define DSCR_DCC_NBLOCK (0 << 20) 46 #define DSCR_DCC_STALL (1 << 20) 47 #define DSCR_DCC_FAST (2 << 20) 48 #define DSCR_ADADISCARD (1 << 19) // ro: processor ignores asynch aborts 49 // set in debug state, DSCR_ADABORT instead 50 #define DSCR_M_DBG_EN (1 << 15) // monitor debug enabled 51 #define DSCR_H_DBG_EN (1 << 14) // halting debug enabled 52 #define DSCR_ITR_EN (1 << 13) // instruction execution enabled 53 #define DSCR_UDCC_DIS (1 << 12) // CP14 user debug disable 54 #define DSCR_INT_DIS (1 << 11) // interrupts disable 55 #define DSCR_DBG_ACK (1 << 10) // force DBGACKm signal HIGH 56 #define DSCR_UND (1 << 8) // sticky undefined bit (wtc) 57 #define DSCR_ADABORT (1 << 7) // sticky asynch data abort bit (wtc) 58 #define DSCR_SDABORT (1 << 6) // sticky synch data abort bit (wtc) 59 #define DSCR_M_MASK (15 << 2) // method-of-entry mask 60 #define DSCR_M_HALT (0 << 2) // halt from DRCR[0] 61 #define DSCR_M_BKPT (1 << 2) // breakpoint 62 #define DSCR_M_EDBGRQ (4 << 2) 63 #define DSCR_M_BKPT_INS (3 << 2) // breakpoint instruction 64 #define DSCR_M_WATCHPT (10 << 2) // synchronous watchpoint 65 #define DSCR_RESTARTED (1 << 1) // 1 = not in debug state 66 #define DSCR_HALTED (1 << 0) // 1 = in debug state 67 68 #define VCR_FIQ (1 << 7) 69 #define VCR_IRQ (1 << 6) 70 #define VCR_DABORT (1 << 4) 71 #define VCR_PABORT (1 << 3) 72 #define VCR_SVC (1 << 2) 73 #define VCR_UND (1 << 1) 74 #define VCR_RESET (1 << 0) 75 76 #define DSCCR_WT_EN (1 << 2) // 0 = force write through in debug state 77 #define DSCCR_IL_EN (1 << 1) // 0 = L1 icache line-fills disabled in debug 78 #define DSCCR_DL_EN (1 << 0) // 0 = L1 dcache line-fills disabled in debug 79 80 #define DRCR_CANCEL (1 << 4) // cancel memory request 81 // processor will abandon inflight mem reqs 82 #define DRCR_PIPEADV (1 << 3) // clear DSCR_PIPEADV 83 #define DRCR_CLR_EXC (1 << 2) // clear sticky exceptions 84 #define DRCR_START_REQ (1 << 1) // request processor restart 85 #define DRCR_HALT_REQ (1 << 0) // request processor halt 86 87 #define PRSR_S_RESET (1 << 3) // sticky reset status 88 #define PRSR_RESET (1 << 2) // reset status 89 #define PRSR_S_PDOWN (1 << 1) // sticky power-down status 90 #define PRSR_PDOWN (1 << 0) // power-down status 91 92 #define LAR_KEY 0xC5ACCE55 // write to LAR to enable debug regs 93 94 #define LSR_32BIT (1 << 2) 95 #define LSR_LOCKED (1 << 1) 96 #define LSR_LOCK_IMPL (1 << 0) 97 98 #define CID_ROM_TABLE 0xB105100D 99 #define CID_CORESIGHT 0xB105900D 100 101 // See: A9 TRM 102 #define PID0_DEBUG 0x000BBC09 103 104 // See: Zynq TRM 105 #define PID0_CTI 0x002BB906 106 #define PID0_PTM 0x001BB950 107 #define PID0_ETB 0x003BB907 108 #define PID0_FTM 0x000C9001 109 #define PID0_FUNNEL 0x001BB908 110 #define PID0_ITM 0x002BB913 111 #define PID0_TPIU 0x004BB912 112 // 0x000BB4A9 113 // 0x000BB9A0 114 // 0x021893B2 115 116 #endif