zynq.c (3283B)
1 // Copyright 2014 Brian Swetland <swetland@frotz.net> 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #include <stdio.h> 16 #include <stdlib.h> 17 #include <string.h> 18 19 #include <unistd.h> 20 #include <fcntl.h> 21 22 #include "v7debug.h" 23 24 #define ZYNQ_DEBUG0_APN 1 25 #define ZYNQ_DEBUG0_BASE 0x80090000 26 #define ZYNQ_DEBUG1_APN 1 27 #define ZYNQ_DEBUG1_BASE 0x80092000 28 29 void *loadfile(const char *fn, u32 *sz) { 30 int fd; 31 off_t end; 32 void *data = NULL; 33 if ((fd = open(fn, O_RDONLY)) < 0) return NULL; 34 if ((end = lseek(fd, 0, SEEK_END)) < 0) goto oops; 35 if (lseek(fd, 0, SEEK_SET) < 0) goto oops; 36 if ((data = malloc(end + 4)) == NULL) goto oops; 37 if (read(fd, data, end) != end) goto oops; 38 close(fd); 39 *sz = end; 40 return data; 41 42 oops: 43 free(data); 44 close(fd); 45 return NULL; 46 } 47 48 int usage(void) { 49 fprintf(stderr, 50 "zynq run <image> download image to 0, resume cpu0 at 0\n" 51 "zynq regs pause both cpus, dump registers, resume\n" 52 "zynq reset reset the SoC\n" 53 "zynq fpga <bitfile> reset fpga and download bitfile to it\n" 54 "\n" 55 ); 56 return -1; 57 } 58 59 int fpga_send_bitfile(JTAG *jtag, void *data, u32 sz, int warmboot); 60 int fpga_prepare_bitfile(u8 *data, u32 sz); 61 62 int main(int argc, char **argv) { 63 JTAG *jtag; 64 DAP *dap; 65 V7DEBUG *d0; 66 V7DEBUG *d1; 67 void *data; 68 u32 sz; 69 70 if (argc < 2) { 71 return usage(); 72 } 73 74 if (jtag_mpsse_open(&jtag)) return -1; 75 jtag_enumerate(jtag); 76 jtag_print_chain(jtag); 77 78 if (!strcmp(argv[1], "fpga")) { 79 if (argc != 3) { 80 return usage(); 81 } 82 if ((data = loadfile(argv[2], &sz)) == NULL) { 83 fprintf(stderr, "error: could not load '%s'\n", argv[2]); 84 return -1; 85 } 86 fpga_prepare_bitfile(data, sz); 87 return fpga_send_bitfile(jtag, data, sz, 0); 88 } 89 90 if ((dap = dap_init(jtag, 0x4ba00477)) == NULL) return -1; 91 if (dap_attach(dap)) return -1; 92 if ((d0 = debug_init(dap, ZYNQ_DEBUG0_APN, ZYNQ_DEBUG0_BASE)) == NULL) return -1; 93 if ((d1 = debug_init(dap, ZYNQ_DEBUG1_APN, ZYNQ_DEBUG1_BASE)) == NULL) return -1; 94 95 if (!strcmp(argv[1], "run")) { 96 if (argc != 3) { 97 return usage(); 98 } 99 if ((data = loadfile(argv[2], &sz)) == NULL) { 100 fprintf(stderr, "error: could not load '%s'\n", argv[2]); 101 return -1; 102 } 103 if (sz > (192*1024)) { 104 fprintf(stderr, "error: image too large\n"); 105 return -1; 106 } 107 if (debug_attach(d0)) return -1; 108 dap_mem_write(dap, 0, 0, data, sz); 109 debug_reg_wr(d0, 15, 0); 110 debug_detach(d0); 111 } else if (!strcmp(argv[1], "regs")) { 112 debug_attach(d0); 113 debug_attach(d1); 114 printf("CPU0:\n"); 115 debug_reg_dump(d0); 116 printf("\nCPU1:\n"); 117 debug_reg_dump(d1); 118 debug_detach(d0); 119 debug_detach(d1); 120 } else if (!strcmp(argv[1], "reset")) { 121 dap_mem_wr32(dap, 0, 0xF8000008, 0xDF0D); 122 dap_mem_wr32(dap, 0, 0xF8000200, 1); 123 } else { 124 return usage(); 125 } 126 127 return 0; 128 } 129