m3dev

cortex m3 debug tools -- superceded by mdebug
git clone http://frotz.net/git/m3dev.git
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nvic.c (1840B)


      1 /* nvic.c
      2  *
      3  * Copyright 2011 Brian Swetland <swetland@frotz.net>
      4  * 
      5  * Licensed under the Apache License, Version 2.0 (the "License");
      6  * you may not use this file except in compliance with the License.
      7  * You may obtain a copy of the License at
      8  *
      9  *     http://www.apache.org/licenses/LICENSE-2.0
     10  *
     11  * Unless required by applicable law or agreed to in writing, software
     12  * distributed under the License is distributed on an "AS IS" BASIS,
     13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
     14  * See the License for the specific language governing permissions and
     15  * limitations under the License.
     16  */
     17 
     18 #include <fw/types.h>
     19 #include <fw/io.h>
     20 
     21 #define NVIC_ICTR		0xE000E004
     22 #define NVIC_SET_ENABLE		0xE000E100
     23 #define NVIC_CLR_ENABLE		0xE000E180
     24 #define NVIC_SET_PENDING	0xE000E200
     25 #define NVIC_CLR_PENDING	0xE000E280
     26 #define NVIC_ACTIVE		0xE000E300
     27 #define NVIC_PRIORITY		0xE000E400
     28 #define NVIC_CPUID		0xE000ED00
     29 #define NVIC_ICSR		0xE000ED04
     30 #define NVIC_VTOR		0xE000ED08
     31 #define NVIC_ARCR		0xE000ED0C
     32 #define NVIC_SYS_CTL		0xE000ED10
     33 #define NVIC_CFG_CTL		0xE000ED14
     34 #define NVIC_HANDLER_PRIORITY	0xE000ED18
     35 #define NVIC_SW_IRQ_TRIGGER	0xE000EF00
     36 
     37 void irq_enable(unsigned n) {
     38 	writel(1 << (n & 31), NVIC_SET_ENABLE + (n >> 5) * 4);
     39 }
     40 
     41 void irq_disable(unsigned n) {
     42 	writel(1 << (n & 31), NVIC_CLR_ENABLE + (n >> 5) * 4);
     43 }
     44 
     45 void irq_assert(unsigned n) {
     46 	writel(1 << (n & 31), NVIC_SET_PENDING + (n >> 5) * 4);
     47 }
     48 
     49 void irq_deassert(unsigned n) {
     50 	writel(1 << (n & 31), NVIC_CLR_PENDING + (n >> 5) * 4);
     51 }
     52 
     53 void irq_set_prio(unsigned n, unsigned p) {
     54 	unsigned shift = (n & 3) * 8;
     55 	unsigned reg = NVIC_PRIORITY + (n >> 2) * 4;
     56 	unsigned val = readl(reg);
     57 	val = val & (~(0xFF << shift));
     58 	val = val | ((n & 0xFF) << shift);
     59 	writel(val, reg);
     60 }
     61 
     62 void irq_set_base(unsigned n) {
     63 	writel(n, NVIC_VTOR);
     64 }
     65