m3dev

cortex m3 debug tools -- superceded by mdebug
git clone http://frotz.net/git/m3dev.git
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start.S (1735B)


      1 /* start.S
      2  *
      3  * Copyright 2011 Brian Swetland <swetland@frotz.net>
      4  * 
      5  * Licensed under the Apache License, Version 2.0 (the "License");
      6  * you may not use this file except in compliance with the License.
      7  * You may obtain a copy of the License at
      8  *
      9  *     http://www.apache.org/licenses/LICENSE-2.0
     10  *
     11  * Unless required by applicable law or agreed to in writing, software
     12  * distributed under the License is distributed on an "AS IS" BASIS,
     13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
     14  * See the License for the specific language governing permissions and
     15  * limitations under the License.
     16  */
     17 
     18 .section .vectors
     19 
     20 .syntax unified
     21 
     22 .globl _start
     23 
     24 #define VECTOR(name) \
     25 __vector__##name: ; \
     26 	.long handle_##name + 1; \
     27 	.weak handle_##name ; \
     28 	.thumb_set handle_##name, deadloop
     29 
     30 #define _IRQ(name) VECTOR(irq_##name)
     31 
     32 _start:
     33 	.long (CONFIG_STACKTOP - 0x10)
     34 	.long reset + 1
     35 	VECTOR(m3_nmi)
     36 	VECTOR(m3_hardfault)
     37 	VECTOR(m3_mmu)
     38 	VECTOR(m3_busfault)
     39 	VECTOR(m3_usagefault)
     40 	VECTOR(m3_reserved_a)
     41 	VECTOR(m3_reserved_b)
     42 	VECTOR(m3_reserved_c)
     43 	VECTOR(m3_reserved_d)
     44 	VECTOR(m3_svc)
     45 	VECTOR(m3_debugmon)
     46 	VECTOR(m3_reserved_e)
     47 	VECTOR(m3_pendsv)
     48 	VECTOR(m3_systick)
     49 .globl  _irq_table
     50 _irq_table:	
     51 #include <arch/irqs.h>
     52 
     53 deadloop:
     54 	/* unlinked vectors point here */
     55 	b .
     56 
     57 reset:
     58 	ldr r1, =__data_init__
     59 	ldr r2, =__data_start__
     60 	ldr r3, =__data_end__
     61 	ldr r4, =__bss_end__
     62 	mov r5, #0
     63 	
     64 	/* if data init and start are the same, skip copy */
     65 	/* this simplifies building-for-ram */
     66 	cmp r1, r2
     67 	bne copydata
     68 	mov r2, r3
     69 	b zerobss
     70 
     71 copydata:
     72 	cmp r2, r3
     73 	beq zerobss
     74 	ldr r0, [r1], #4
     75 	str r0, [r2], #4
     76 	b copydata
     77 zerobss:
     78 	cmp r2, r4
     79 	beq tmp_main
     80 	str r5, [r2], #4
     81 	b zerobss
     82 
     83 tmp_main:
     84 	b main