m3dev

cortex m3 debug tools -- superceded by mdebug
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usb-v2.h (2919B)


      1 #ifndef __ARCH_LPC13XX_USB_V2_H
      2 #define __ARCH_LPC13XX_USB_V2_H
      3 
      4 #define USB_BASE		0x40080000
      5 #define USB_SRAM		0x20004000
      6 #define USB_SRAM_SIZE		0x800
      7 
      8 #define USB_DEVCMDSTAT		(USB_BASE + 0x00)
      9 #define  USB_DEVCMDSTAT_DEV_ADDR(x)	((x) & 0x7f)
     10 #define  USB_DEVCMDSTAT_DEV_EN		(1 << 7)
     11 #define  USB_DEVCMDSTAT_SETUP		(1 << 8)
     12 #define  USB_DEVCMDSTAT_PLL_ON		(1 << 9)
     13 #define  USB_DEVCMDSTAT_LPM_SUP		(1 << 11)
     14 #define  USB_DEVCMDSTAT_INTONNAK_AO	(1 << 12)
     15 #define  USB_DEVCMDSTAT_INTONNAK_AI	(1 << 13)
     16 #define  USB_DEVCMDSTAT_INTONNAK_CO	(1 << 14)
     17 #define  USB_DEVCMDSTAT_INTONNAK_CI	(1 << 15)
     18 #define  USB_DEVCMDSTAT_DCON		(1 << 16)
     19 #define  USB_DEVCMDSTAT_DSUS		(1 << 17)
     20 #define  USB_DEVCMDSTAT_LPM_SUS		(1 << 19)
     21 #define  USB_DEVCMDSTAT_LPM_REWP	(1 << 20)
     22 #define  USB_DEVCMDSTAT_DCON_C		(1 << 24)
     23 #define  USB_DEVCMDSTAT_DSUS_C		(1 << 25)
     24 #define  USB_DEVCMDSTAT_DRES_C		(1 << 26)
     25 #define  USB_DEVCMDSTAT_VBUSDEBOUNCED	(1 << 28)
     26 
     27 #define USB_INFO		(USB_BASE + 0x04)
     28 #define  USB_INFO_FRAME_NR(reg)		((reg) & 0x7ff)
     29 #define  USB_INFO_ERR_CODE(reg)		(((reg) >> 11) & 0xf)
     30 
     31 #define USB_EPLISTSTART		(USB_BASE + 0x08) /* must be 256 byte aligned */
     32 #define USB_DATABUFSTART	(USB_BASE + 0x0C) /* musb be 0x400000 alignd */
     33 
     34 #define USB_LPM			(USB_BASE + 0x10)
     35 
     36 #define USB_EPSKIP		(USB_BASE + 0x14)
     37 #define USB_EPINUSE		(USB_BASE + 0x18)
     38 #define USB_EPBUFCFG		(USB_BASE + 0x1C)
     39 
     40 #define USB_INTSTAT		(USB_BASE + 0x20)
     41 #define USB_INTEN		(USB_BASE + 0x24)
     42 #define USB_INTSETSTAT		(USB_BASE + 0x28)
     43 #define USB_INTROUTING		(USB_BASE + 0x2C)
     44 #define  USB_INT_EP0OUT			(1 << 0)
     45 #define  USB_INT_EP0IN			(1 << 1)
     46 #define  USB_INT_EP1OUT			(1 << 2)
     47 #define  USB_INT_EP1IN			(1 << 3)
     48 #define  USB_INT_EP2OUT			(1 << 4)
     49 #define  USB_INT_EP2IN			(1 << 5)
     50 #define  USB_INT_EP3OUT			(1 << 6)
     51 #define  USB_INT_EP3IN			(1 << 7)
     52 #define  USB_INT_EP4OUT			(1 << 8)
     53 #define  USB_INT_EP4IN			(1 << 9)
     54 #define  USB_INT_FRAME_INT		(1 << 30)
     55 #define  USB_INT_DEV_INT		(1 << 31)
     56 
     57 #define USB_EPTOGGLE		(USB_BASE + 0x34)
     58 
     59 #define USB_EP_LIST_BUF_ADDR(addr)		(((unsigned)(addr) >> 6) & 0xffff)
     60 #define USB_EP_LIST_BUF_SIZE(size)		(((size) & 0x3ff) << 16)
     61 #define USB_EP_LIST_GET_BUF_SIZE(reg)		(((reg) >> 16) & 0x3ff)
     62 #define USB_EP_LIST_TYPE			(1 << 26) /* Endpoint Type */
     63 #define USB_EP_LIST_RF_TV			(1 << 27) /* Rate Feedback/Toggle value */
     64 #define USB_EP_LIST_TR				(1 << 28) /* Toggle Reset */
     65 #define USB_EP_LIST_STALL			(1 << 29) /* Stall */
     66 #define USB_EP_LIST_DISABLED			(1 << 30) /* Disabled */
     67 #define USB_EP_LIST_ACTIVE			(1 << 31) /* Active */
     68 
     69 enum {
     70 	EP_LIST_EP0_OUT = 0,
     71 	EP_LIST_SETUP,
     72 	EP_LIST_EP0_IN,
     73 	EP_LIST_RES,
     74 	EP_LIST_EP1_OUT0,
     75 	EP_LIST_EP1_OUT1,
     76 	EP_LIST_EP1_IN0,
     77 	EP_LIST_EP1_IN1,
     78 	EP_LIST_EP2_OUT0,
     79 	EP_LIST_EP2_OUT1,
     80 	EP_LIST_EP2_IN0,
     81 	EP_LIST_EP2_IN1,
     82 	EP_LIST_EP3_OUT0,
     83 	EP_LIST_EP3_OUT1,
     84 	EP_LIST_EP3_IN0,
     85 	EP_LIST_EP3_IN1,
     86 	EP_LIST_EP4_OUT0,
     87 	EP_LIST_EP4_OUT1,
     88 	EP_LIST_EP4_IN0,
     89 	EP_LIST_EP4_IN1,
     90 };
     91 
     92 #endif