rswdp.h (4943B)
1 /* rswdp.h - remote serial wire debug protocol 2 * 3 * Copyright 2011 Brian Swetland <swetland@frotz.net> 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 */ 17 18 /* Remote Serial Wire Debug Protocol */ 19 20 #ifndef _RSWDP_PROTOCOL_H_ 21 #define _RSWDP_PROTOCOL_H_ 22 23 /* Basic framing: 24 * - host and device exchange "transactions" consisting of 25 * some number of "messages". 26 * - each "message" has a 32bit header and may have 0 or more 27 * 32bit words of payload 28 * - a transaction may not exceed 4K (1024 words) 29 * - a transaction is sent in a series of USB BULK packets 30 * - the final packet must be a short packet unless the 31 * transaction is exactly 4K in length 32 * - packets must be a multiple of 4 bytes 33 * - the first message in a transaction must be 34 * CMD_TXN_START or CMD_TXN_ASYNC 35 */ 36 37 #define RSWD_MSG(cmd,op,n) ((((cmd)&0xFF) << 24) | (((op) & 0xFF)<<16) | ((n) & 0xFFFF)) 38 #define RSWD_MSG_CMD(n) (((n) >> 24) & 0xFF) 39 #define RSWD_MSG_OP(n) (((n) >> 16) & 0xFF) 40 #define RSWD_MSG_ARG(n) ((n) & 0xFFFF) 41 42 #define RSWD_TXN_START(seq) (0xAA770000 | ((seq) & 0xFFFF)) 43 #define RSWD_TXN_ASYNC (0xAA001111) 44 45 /* valid: either */ 46 #define CMD_NULL 0x00 /* used for padding */ 47 48 /* valid: host to target */ 49 #define CMD_SWD_WRITE 0x01 /* op=addr arg=count payload: data x count */ 50 #define CMD_SWD_READ 0x02 /* op=addr arg=count payload: data x count */ 51 #define CMD_SWD_DISCARD 0x03 /* op=addr arg=count payload: none (discards) */ 52 #define CMD_ATTACH 0x04 /* do swdp reset/connect handshake */ 53 #define CMD_RESET 0x05 /* arg=1 -> assert RESETn, otherwise deassert */ 54 #define CMD_DOWNLOAD 0x06 /* arg=wordcount, payload: addr x 1, data x n */ 55 #define CMD_EXECUTE 0x07 /* payload: addr x 1 */ 56 #define CMD_TRACE 0x08 /* op=tracebits n=0 */ 57 #define CMD_BOOTLOADER 0x09 /* return to bootloader for reflashing */ 58 #define CMD_SET_CLOCK 0x0A /* set SWCLK rate to n khz */ 59 #define CMD_SWO_CLOCK 0x0B /* set SWOCLK rate to n khz, 0 = disable SWO */ 60 61 /* valid: target to host */ 62 #define CMD_STATUS 0x10 /* op=errorcode, arg=commands since last TXN_START */ 63 #define CMD_SWD_DATA 0x11 /* op=0 arg=count, payload: data x count */ 64 #define CMD_SWO_DATA 0x12 /* op=0 arg=count, payload: count * 4 bytes */ 65 66 /* valid: target to host async */ 67 #define CMD_DEBUG_PRINT 0x20 /* arg*4 bytes of ascii debug output */ 68 69 /* valid: bidirectional query/config messages */ 70 #define CMD_VERSION 0x30 /* arg=bcdversion (0x0100 etc) */ 71 #define CMD_BUILD_STR 0x31 /* arg=wordcount, payload = asciiz */ 72 #define CMD_BOARD_STR 0x32 /* arg=wordcount, payload = asciiz */ 73 #define CMD_RX_MAXDATA 0x33 /* arg=bytes, declares senders rx buffer size */ 74 #define CMD_CLOCK_KHZ 0x34 /* arg=khz, reports active clock rate */ 75 76 /* CMD_STATUS error codes */ 77 #define ERR_NONE 0 78 #define ERR_INTERNAL 1 79 #define ERR_TIMEOUT 2 80 #define ERR_IO 3 81 #define ERR_PARITY 4 82 83 #define RSWD_VERSION 0x0100 84 85 /* CMD_SWD_OP operations - combine for direct AP/DP io */ 86 #define OP_RD 0x00 87 #define OP_WR 0x01 88 #define OP_DP 0x00 89 #define OP_AP 0x02 90 #define OP_X0 0x00 91 #define OP_X4 0x04 92 #define OP_X8 0x08 93 #define OP_XC 0x0C 94 95 /* DP registers */ 96 #define DP_IDCODE (OP_DP|OP_X0) 97 #define DP_ABORT (OP_DP|OP_X0) 98 #define DP_DPCTRL (OP_DP|OP_X4) 99 #define DP_RESEND (OP_DP|OP_X8) 100 #define DP_SELECT (OP_DP|OP_X8) 101 #define DP_BUFFER (OP_DP|OP_XC) 102 103 /* AHB AP registers */ 104 #define AHB_CSW 0x00 105 #define AHB_TAR 0x04 106 #define AHB_DRW 0x0C 107 #define AHB_BD0 0x10 108 #define AHB_BD1 0x14 109 #define AHB_BD2 0x18 110 #define AHB_BD3 0x20 111 #define AHB_ROM_ADDR 0xF8 112 #define AHB_IDR 0xFC 113 114 #define AHB_CSW_MCORE (0 << 29) 115 #define AHB_CSW_MDEBUG (1 << 29) 116 #define AHB_CSW_USER (0 << 25) 117 #define AHB_CSW_PRIV (1 << 25) 118 #define AHB_CSW_DBG_EN (1 << 6) 119 #define AHB_CSW_INC_NONE (0 << 4) 120 #define AHB_CSW_INC_SINGLE (1 << 4) 121 #define AHB_CSWINC_PACKED (2 << 4) 122 #define AHB_CSW_8BIT (0 << 0) 123 #define AHB_CSW_16BIT (1 << 0) 124 #define AHB_CSW_32BIT (2 << 0) 125 126 /* Core Debug registers */ 127 #define CDBG_CSR 0xE000EDF0 128 #define CDBG_REG_ADDR 0xE000EDF4 129 #define CDBG_REG_DATA 0xE000EDF8 130 #define CDBG_EMCR 0xE000EDFC 131 132 #define CDBG_CSR_KEY 0xA05F0000 133 #define CDBG_S_RESET_ST (1 << 25) 134 #define CDBG_S_RETIRE_ST (1 << 24) 135 #define CDBG_S_LOCKUP (1 << 19) 136 #define CDBG_S_SLEEP (1 << 18) 137 #define CDBG_S_HALT (1 << 17) 138 #define CDBG_S_REGRDY (1 << 16) 139 #define CDBG_C_SNAPSTALL (1 << 5) 140 #define CDBG_C_MASKINTS (1 << 3) 141 #define CDBG_C_STEP (1 << 2) 142 #define CDBG_C_HALT (1 << 1) 143 #define CDBG_C_DEBUGEN (1 << 0) 144 145 #define IDCODE_M3 0x1BA01477 146 147 #endif