m3dev

cortex m3 debug tools -- superceded by mdebug
git clone http://frotz.net/git/m3dev.git
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unused.c (2893B)


      1 /* unused.c
      2  *
      3  * Copyright 2011 Brian Swetland <swetland@frotz.net>
      4  * 
      5  * Licensed under the Apache License, Version 2.0 (the "License");
      6  * you may not use this file except in compliance with the License.
      7  * You may obtain a copy of the License at
      8  *
      9  *     http://www.apache.org/licenses/LICENSE-2.0
     10  *
     11  * Unless required by applicable law or agreed to in writing, software
     12  * distributed under the License is distributed on an "AS IS" BASIS,
     13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
     14  * See the License for the specific language governing permissions and
     15  * limitations under the License.
     16  */
     17 
     18 /* tidbits from when the device side was smarter */
     19 /* may be useful again someday */
     20 
     21 static unsigned prevaddr;
     22 
     23 static unsigned char ap_rr[4] = { RD_AP0, RD_AP1, RD_AP2, RD_AP3 };
     24 static unsigned char ap_wr[4] = { WR_AP0, WR_AP1, WR_AP2, WR_AP3 };
     25 
     26 unsigned swdp_ap_read(unsigned addr) {
     27 	if ((addr & 0xF0) != prevaddr) {
     28 		swdp_write(WR_SELECT, (addr & 0xF0) | (0 << 24));
     29 		prevaddr = addr & 0xF0;
     30 	}
     31 	swdp_read(ap_rr[(addr >> 2) & 3]);
     32 	return swdp_read(RD_BUFFER);
     33 }
     34 
     35 unsigned swdp_ap_write(unsigned addr, unsigned value) {
     36 	if ((addr & 0xF0) != prevaddr) {
     37 		swdp_write(WR_SELECT, (addr & 0xF0) | (0 << 24));
     38 		prevaddr = addr & 0xF0;
     39 	}
     40 	swdp_write(ap_wr[(addr >> 2) & 3], value);
     41 }
     42 
     43 void crap(void) {
     44 	/* invalidate AP address cache */
     45 	prevaddr = 0xFF;
     46 
     47 	printx("IDCODE= %x\n", idcode);
     48 
     49 	swdp_write(WR_ABORT, 0x1E); // clear any stale errors
     50 	swdp_write(WR_DPCTRL, (1 << 28) | (1 << 30)); // POWER UP
     51 	n = swdp_read(RD_DPCTRL);
     52 	printx("DPCTRL= %x\n", n);
     53 
     54 	/* configure for 32bit IO */
     55 	swdp_ap_write(AHB_CSW, AHB_CSW_MDEBUG | AHB_CSW_PRIV |
     56 		AHB_CSW_PRIV | AHB_CSW_DBG_EN | AHB_CSW_32BIT);
     57 
     58 	printx("ROMADDR= %x", swdp_ap_read(AHB_ROM_ADDR));
     59 }
     60 
     61 unsigned swdp_core_read(unsigned n) {
     62 	swdp_ahb_write(CDBG_REG_ADDR, n);
     63 	return swdp_ahb_read(CDBG_REG_DATA);
     64 }
     65 
     66 void swdp_core_halt(void) {
     67 	unsigned n = swdp_ahb_read(CDBG_CSR);
     68 	swdp_ahb_write(CDBG_CSR, 
     69 		CDBG_CSR_KEY | (n & 0x3F) |
     70 		CDBG_C_HALT | CDBG_C_DEBUGEN);
     71 }
     72 
     73 void swdp_core_resume(void) {
     74 	unsigned n = swdp_ahb_read(CDBG_CSR);
     75 	swdp_ahb_write(CDBG_CSR,
     76 		CDBG_CSR_KEY | (n & 0x3C));
     77 }
     78 
     79 unsigned swdp_ahb_read(unsigned addr) {
     80 	swdp_ap_write(AHB_TAR, addr);
     81 	return swdp_ap_read(AHB_DRW);
     82 }
     83 
     84 void swdp_ahb_write(unsigned addr, unsigned value) {
     85 	swdp_ap_write(AHB_TAR, addr);
     86 	swdp_ap_write(AHB_DRW, value);
     87 }
     88 
     89 void swdp_test(void) {
     90 	unsigned n;
     91 	swdp_reset();
     92 
     93 
     94 	for (n = 0x20000000; n < 0x20000020; n += 4) {
     95 		swdp_ap_write(AHB_TAR, n);
     96 		printx("%x: %x\n", n, swdp_ap_read(AHB_DRW));
     97 	}
     98 
     99 	swdp_ap_write(AHB_TAR, 0xE000EDF0);
    100 	swdp_ap_write(AHB_DRW, 0xA05F0003);
    101 
    102 	swdp_ap_write(AHB_TAR, 0x20000000);
    103 	swdp_ap_write(AHB_DRW, 0x12345678);
    104 	printx("DPCTRL= %x\n", swdp_read(RD_DPCTRL));
    105 	printx("DPCTRL= %x\n", swdp_read(RD_DPCTRL));
    106 	swdp_read(RD_BUFFER);
    107 	swdp_read(RD_BUFFER);
    108 }
    109