arm-v7m.h (7047B)
1 #ifndef _ARM_V7M_H_ 2 #define _ARM_V7M_H_ 3 4 // ---- debug registers ----------------- 5 #define DHCSR 0xE000EDF0 // Debug Halting Ctrl/Stat 6 #define DCRSR 0xE000EDF4 // Debug Core Reg Select 7 #define DCRDR 0xE000EDF8 // Debug Core Reg Data 8 #define DEMCR 0xE000EDFC // Debug Exception & Monitor Ctrl 9 10 #define DHCSR_DBGKEY 0xA05F0000 11 #define DHCSR_S_RESET_ST (1 << 25) // CPU Reset Since Last Read (CoR) 12 #define DHCSR_S_RETIRE_ST (1 << 24) // Inst Retired Since Last Read (CoR) 13 #define DHCSR_S_LOCKUP (1 << 19) // CPU is locked up / unrecov excpt 14 #define DHCSR_S_SLEEP (1 << 18) // CPU is Sleeping 15 #define DHCSR_S_HALT (1 << 17) // CPU is Halted 16 #define DHCSR_S_REGRDY (1 << 16) // 0:DCRSR Written 1:DCRSR TXN Done 17 #define DHCSR_C_SNAPSTALL (1 << 5) // Allow Imprecise Debug Entry 18 #define DHCSR_C_MASKINTS (1 << 3) // Mask PendSV, SysTick, and Ext IRQs 19 // C_HALT must already be and remain 1 20 #define DHCSR_C_STEP (1 << 2) // Enable Single Step 21 #define DHCSR_C_HALT (1 << 1) // Halt CPU 22 #define DHCSR_C_DEBUGEN (1 << 0) // Enable Halting Debug 23 24 #define DCRSR_REG_WR (1 << 16) // Write 25 26 #define DEMCR_TRCENA (1 << 24) // Enable DWT and ITM 27 #define DEMCR_MON_REQ (1 << 19) // HW does not use, SW Sem Bit 28 #define DEMCR_MON_STEP (1 << 18) // Set Step Request Pending (in Mon Mode) 29 #define DEMCR_MON_PEND (1 << 17) // Set DebugMonitor Exception Pending 30 #define DEMCR_MON_EN (1 << 16) // Enable DebugMonitor Exception 31 32 #define DEMCR_VC_HARDERR (1 << 10) // Vector Catch: HardFault Exception 33 #define DEMCR_VC_INTERR (1 << 9) // Vector Catch: Exception Entry / Return 34 #define DEMCR_VC_BUSERR (1 << 8) // Vector Catch: BusFault Exception 35 #define DEMCR_VC_STATERR (1 << 7) // Vector Catch: UsageFault State Error 36 #define DEMCR_VC_CHKERR (1 << 6) // Vector Catch: UsageFault Check Error 37 #define DEMCR_VC_NOCPERR (1 << 5) // Vector Catch: Coprocessor Access 38 #define DEMCR_VC_MMERR (1 << 4) // Vector Catch: MemManage Exception 39 #define DEMCR_VC_CORERESET (1 << 0) // Vector Catch: Core Reset 40 41 // ---- fault status registers ----------- 42 #define CFSR 0xE000ED28 // Configurable Fault Status Register 43 #define HFSR 0xE000ED2C // Hard Fault Status Register 44 #define DFSR 0xE000ED30 // Debug Fault Status Register 45 #define MMFAR 0xE000ED34 // MM Fault Address Register 46 #define BFAR 0xE000ED38 // Bus Fault Address Register 47 #define AFSR 0xE000ED3C // Aux Fault Status Register (Impl Defined) 48 49 #define CFSR_IACCVIOL (1 << 0) // Inst Access Violation 50 #define CFSR_DACCVIOL (1 << 1) // Data Access Violation 51 #define CFSR_MUNSTKERR (1 << 3) // Derived MM Fault on Exception Return 52 #define CFSR_MSTKERR (1 << 4) // Derived MM Fault on Exception Entry 53 #define CFSR_MLSPERR (1 << 5) // MM Fault During Lazy FP Save 54 #define CFSR_MMARVALID (1 << 7) // MMFAR has valid contents 55 56 #define CFSR_IBUSERR (1 << 8) // Bus Fault on Instruction Prefetch 57 #define CFSR_PRECISERR (1 << 9) // Precise Data Access Error, Addr in BFAR 58 #define CFSR_IMPRECISERR (1 << 10) // Imprecise Data Access Error 59 #define CFSR_UNSTKERR (1 << 11) // Derived Bus Fault on Exception Return 60 #define CFSR_STKERR (1 << 12) // Derived Bus Fault on Exception Entry 61 #define CFSR_LSPERR (1 << 13) // Bus Fault During Lazy FP Save 62 #define CFSR_BFARVALID (1 << 15) // BFAR has valid contents 63 64 #define CFSR_UNDEFINSTR (1 << 16) // Undefined Instruction Usage Fault 65 #define CFSR_INVSTATE (1 << 17) // EPSR.T or ESPR.IT invalid 66 #define CFSR_INVPC (1 << 18) // Integrity Check Error on EXC_RETURN 67 #define CFSR_NOCP (1 << 19) // Coprocessor Error 68 #define CFSR_UNALIGNED (1 << 24) // Unaligned Access Error 69 #define CFSR_DIVBYZERO (1 << 25) // Divide by Zero (when CCR.DIV_0_TRP set) 70 71 #define CFSR_ALL 0x030FBFBD // all fault bits 72 73 // Write 1 to Clear Status Bits 74 #define DFSR_HALTED (1 << 0) // DHCSR C_HALT or C_STEP Request 75 #define DFSR_BKPT (1 << 1) // BKPT instruction or FPB match 76 #define DFSR_DWTTRAP (1 << 2) // DWT Debug Event 77 #define DFSR_VCATCH (1 << 3) // Vector Catch Event 78 #define DFSR_EXTERNAL (1 << 4) // External Debug Event 79 80 #define DFSR_ALL 0x0000001F // all fault bits 81 82 83 #define HFSR_VECTTBL (1 << 1) // Vector Table Read Fault 84 #define HFSR_FORCED (1 << 30) // Configurable-Priority Exception Escalated 85 #define HFSR_DEBUGEVT (1 << 31) // Debug Event Occurred (and halting debug off) 86 87 #define HFSR_ALL 0xC0000002 // all fault bits 88 89 // ---- Data Watchpoint and Trace -------- 90 #define DWT_CTRL 0xE0001000 // Control Register 91 #define DWT_CYCCNT 0xE0001004 // Cycle Count Register 92 #define DWT_CPICNT 0xE0001008 // CPI Count Register 93 #define DWT_EXCCNT 0xE000100C // Exception Overhead Count Register 94 #define DWT_SLEEPCNT 0xE0001010 // Sleep Count Register 95 #define DWT_LSUCNT 0xE0001014 // LSU Count Register 96 #define DWT_FOLDCNT 0xE0001018 // Folded Instruction Count Register 97 #define DWT_PCSR 0xE000101C // Program Counter Sample Register 98 #define DWT_COMP(n) (0xE0001020 + (n) * 0x10) 99 #define DWT_MASK(n) (0xE0001024 + (n) * 0x10) 100 #define DWT_FUNC(n) (0xE0001028 + (n) * 0x10) 101 102 // ---- DWT_CTRL bits --------- 103 #define DWT_CYCCNTENA (1 << 0) // Enable Cycle Counter 104 #define DWT_POSTPRESET(n) (((n) & 15) << 1) 105 #define DWT_POSTINIT(n) (((n) & 15) << 5) 106 #define DWT_CYCTAP (1 << 9) // 0: POSTCNT tap at CYCCNT[6], 1: at [10] 107 #define DWT_SYNCTAP_DISABLE (0 << 10) 108 #define DWT_SYNCTAP_BIT24 (1 << 10) 109 #define DWT_SYNCTAP_BIT26 (2 << 10) 110 #define DWT_SYNCTAP_BIT28 (3 << 10) 111 #define DWT_PCSAMPLENA (1 << 12) // Enable POSTCNT as timer for PC Sample Pkts 112 #define DWT_EXCTRCENA (1 << 16) // Enable Exception Trace 113 #define DWT_CPIEVTENA (1 << 17) // Enable CPI Counter Overflow Events 114 #define DWT_EXCEVTENA (1 << 18) // Enable Exception Overhead Counter Ovf Evt 115 #define DWT_SLEEPEVTENA (1 << 19) // Enable Sleep Counter Ovf Evt 116 #define DWT_LSUEVTENA (1 << 20) // Enable LSU Counter Ovf Evt 117 #define DWT_FOLDEVTENA (1 << 21) // Enable Folded Instruction Counter Ovf Evt 118 #define DWT_CYCEVTENA (1 << 22) // Enable POSTCNT Undererflow Packets 119 #define DWT_NOPRFCNT (1 << 24) // 1: No Profiling Counters 120 #define DWT_NOCYCCNT (1 << 25) // 1: No Cycle Counter 121 #define DWT_NOEXTTRIG (1 << 26) // 1: No External Match Signals 122 #define DWT_NOTRCPKT (1 << 27) // 1: No Trace Sampling and Exception Tracing 123 #define DWT_NUMCOMP(v) ((v) >> 28) 124 125 // ---- DWT_FUNC(n) bits ------ 126 127 #define DWT_FN_DISABLED 0x0 128 129 #define DWT_FN_WATCH_PC 0x4 130 #define DWT_FN_WATCH_RD 0x5 131 #define DWT_FN_WATCH_WR 0x6 132 #define DWT_FN_WATCH_RW 0x7 133 134 #define DWT_EMITRANGE (1 << 5) // 1: Enable Data Trace Address Packet Gen 135 #define DWT_CYCMATCH (1 << 7) // 1: Cycle Count Comparison (only for COMP0) 136 #define DWT_DATAVMATCH (1 << 8) // 0: Address Comparison 1: Value Comparison 137 #define DWT_LNK1ENA (1 << 9) // RO: 1: Linked Comparator Supported 138 #define DWT_DATAVSIZE_BYTE (0 << 10) 139 #define DWT_DATAVSIZE_HALF (1 << 10) 140 #define DWT_DATAVSIZE_WORD (2 << 10) 141 #define DWT_DATAVADDR0(n) (((n) & 15) << 12) 142 #define DWT_DATAVADDR1(n) (((n) & 15) << 16) 143 #define DWT_MATCHED (1 << 24) // Matched since last read. Cleared on read. 144 145 #endif 146