mdebug

cortex m series debugger
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rswdp.h (5584B)


      1 /* rswdp.h - remote serial wire debug protocol
      2  *
      3  * Copyright 2011 Brian Swetland <swetland@frotz.net>
      4  *
      5  * Licensed under the Apache License, Version 2.0 (the "License");
      6  * you may not use this file except in compliance with the License.
      7  * You may obtain a copy of the License at
      8  *
      9  *     http://www.apache.org/licenses/LICENSE-2.0
     10  *
     11  * Unless required by applicable law or agreed to in writing, software
     12  * distributed under the License is distributed on an "AS IS" BASIS,
     13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
     14  * See the License for the specific language governing permissions and
     15  * limitations under the License.
     16  */
     17 
     18 /* Remote Serial Wire Debug Protocol */
     19 
     20 #ifndef _RSWDP_PROTOCOL_H_
     21 #define _RSWDP_PROTOCOL_H_
     22 
     23 /* Basic framing:
     24  * - host and device exchange "transactions" consisting of
     25  *   some number of "messages".
     26  * - each "message" has a 32bit header and may have 0 or more
     27  *   32bit words of payload
     28  * - a transaction may not exceed 4K (1024 words)
     29  * - a transaction is sent in a series of USB BULK packets
     30  * - the final packet must be a short packet unless the
     31  *   transaction is exactly 4K in length
     32  * - packets must be a multiple of 4 bytes
     33  * - the first message in a transaction must be
     34  *   CMD_TXN_START or CMD_TXN_ASYNC
     35  */
     36 
     37 #define RSWD_MSG(cmd,op,n)	((((cmd)&0xFF) << 24) | (((op) & 0xFF)<<16) | ((n) & 0xFFFF))
     38 #define RSWD_MSG_CMD(n)		(((n) >> 24) & 0xFF)
     39 #define RSWD_MSG_OP(n)		(((n) >> 16) & 0xFF)
     40 #define RSWD_MSG_ARG(n)		((n) & 0xFFFF)
     41 
     42 #define RSWD_TXN_START(seq)	(0xAA770000 | ((seq) & 0xFFFF))
     43 #define RSWD_TXN_ASYNC		(0xAA001111)
     44 
     45 /* valid: either */
     46 #define CMD_NULL	0x00 /* used for padding */
     47 
     48 /* valid: host to target */
     49 #define CMD_SWD_WRITE	0x01 /* op=addr arg=count payload: data x count */
     50 #define CMD_SWD_READ	0x02 /* op=addr arg=count payload: data x count */
     51 #define CMD_SWD_DISCARD	0x03 /* op=addr arg=count payload: none (discards) */
     52 #define CMD_ATTACH	0x04 /* do swdp reset/connect handshake */
     53 #define CMD_RESET	0x05 /* arg=1 -> assert RESETn, otherwise deassert */
     54 #define CMD_DOWNLOAD	0x06 /* arg=wordcount, payload: addr x 1, data x n */
     55 #define CMD_EXECUTE	0x07 /* payload: addr x 1 */
     56 #define CMD_TRACE	0x08 /* op=tracebits n=0 */
     57 #define CMD_BOOTLOADER	0x09 /* return to bootloader for reflashing */
     58 #define CMD_SET_CLOCK	0x0A /* set SWCLK rate to n khz */
     59 #define CMD_SWO_CLOCK	0x0B /* set SWOCLK rate to n khz, 0 = disable SWO */
     60 #define CMD_JTAG_IO	0x0C /* op=0, arg=bitcount, data x (count/32) * 2 */
     61 			     /* tms, tdi word pairs per 32bits */
     62 
     63 /* ATTACH ops */
     64 #define ATTACH_SWD_RESET 0
     65 #define ATTACH_JTAG_TO_SWD 1
     66 #define ATTACH_DORMANT_TO_SWD 2
     67 #define ATTACH_SWD_TO_DORMANT 3
     68 
     69 /* valid: target to host */
     70 #define CMD_STATUS	0x10 /* op=errorcode, arg=commands since last TXN_START */
     71 #define CMD_SWD_DATA	0x11 /* op=0 arg=count, payload: data x count */
     72 #define CMD_SWO_DATA	0x12 /* op=0 arg=count, payload: ((count+3)/4) words */
     73 #define CMD_JTAG_DATA	0x14 /* op=0 arg=bitcount, payload: (bitcount/32) words */
     74 
     75 /* valid: target to host async */
     76 #define CMD_DEBUG_PRINT	0x20 /* arg*4 bytes of ascii debug output */
     77 
     78 /* valid: bidirectional query/config messages */
     79 #define CMD_VERSION	0x30 /* arg=bcdversion (0x0100 etc) */
     80 #define CMD_BUILD_STR	0x31 /* arg=wordcount, payload = asciiz */
     81 #define CMD_BOARD_STR	0x32 /* arg=wordcount, payload = asciiz */
     82 #define CMD_RX_MAXDATA	0x33 /* arg=bytes, declares senders rx buffer size */
     83 #define CMD_CLOCK_KHZ	0x34 /* arg=khz, reports active clock rate */
     84 
     85 /* CMD_STATUS error codes */
     86 #define ERR_NONE	0
     87 #define ERR_INTERNAL	1
     88 #define ERR_TIMEOUT	2
     89 #define ERR_IO		3
     90 #define ERR_PARITY	4
     91 
     92 #define RSWD_VERSION		0x0101
     93 
     94 #define RSWD_VERSION_1_0	0x0100
     95 #define RSWD_VERSION_1_1	0x0101
     96 
     97 // Pre-1.0
     98 //  - max packet size fixed at 2048 bytes
     99 //
    100 // Version 1.0
    101 // - CMD_VERSION, CMD_BUILD_STR, CMD_BOARD_STR, CMD_RX_MAXDATA,
    102 //   CMD_CLOCK_KHZ added
    103 //
    104 // Version 1.1
    105 // - CMD_SWO_DATA arg is now byte count, not word count
    106 
    107 /* CMD_SWD_OP operations - combine for direct AP/DP io */
    108 #define OP_RD 0x00
    109 #define OP_WR 0x01
    110 #define OP_DP 0x00
    111 #define OP_AP 0x02
    112 #define OP_X0 0x00
    113 #define OP_X4 0x04
    114 #define OP_X8 0x08
    115 #define OP_XC 0x0C
    116 
    117 /* DP registers */
    118 #define DP_IDCODE	(OP_DP|OP_X0)
    119 #define DP_ABORT	(OP_DP|OP_X0)
    120 #define DP_DPCTRL	(OP_DP|OP_X4)
    121 #define DP_RESEND	(OP_DP|OP_X8)
    122 #define DP_SELECT	(OP_DP|OP_X8)
    123 #define DP_BUFFER	(OP_DP|OP_XC)
    124 
    125 /* AHB AP registers */
    126 #define AHB_CSW		0x00
    127 #define AHB_TAR		0x04
    128 #define AHB_DRW		0x0C
    129 #define AHB_BD0		0x10
    130 #define AHB_BD1		0x14
    131 #define AHB_BD2		0x18
    132 #define AHB_BD3		0x20
    133 #define AHB_ROM_ADDR	0xF8
    134 #define AHB_IDR		0xFC
    135 
    136 #define AHB_CSW_MCORE		(0 << 29)
    137 #define AHB_CSW_MDEBUG		(1 << 29)
    138 #define AHB_CSW_USER		(0 << 25)
    139 #define AHB_CSW_PRIV		(1 << 25)
    140 #define AHB_CSW_DBG_EN		(1 << 6)
    141 #define AHB_CSW_INC_NONE	(0 << 4)
    142 #define AHB_CSW_INC_SINGLE	(1 << 4)
    143 #define AHB_CSWINC_PACKED	(2 << 4)
    144 #define AHB_CSW_8BIT		(0 << 0)
    145 #define AHB_CSW_16BIT		(1 << 0)
    146 #define AHB_CSW_32BIT		(2 << 0)
    147 
    148 /* Core Debug registers */
    149 #define CDBG_CSR		0xE000EDF0
    150 #define CDBG_REG_ADDR		0xE000EDF4
    151 #define CDBG_REG_DATA		0xE000EDF8
    152 #define CDBG_EMCR		0xE000EDFC
    153 
    154 #define CDBG_CSR_KEY		0xA05F0000
    155 #define CDBG_S_RESET_ST		(1 << 25)
    156 #define CDBG_S_RETIRE_ST	(1 << 24)
    157 #define CDBG_S_LOCKUP		(1 << 19)
    158 #define CDBG_S_SLEEP		(1 << 18)
    159 #define CDBG_S_HALT		(1 << 17)
    160 #define CDBG_S_REGRDY		(1 << 16)
    161 #define CDBG_C_SNAPSTALL	(1 << 5)
    162 #define CDBG_C_MASKINTS		(1 << 3)
    163 #define CDBG_C_STEP		(1 << 2)
    164 #define CDBG_C_HALT		(1 << 1)
    165 #define CDBG_C_DEBUGEN		(1 << 0)
    166 
    167 #define IDCODE_M3 0x1BA01477
    168 
    169 #endif