mdebug

cortex m series debugger
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dap-registers.h (2284B)


      1 #ifndef _DAP_REGISTERS_H_
      2 #define _DAP_REGISTERS_H_
      3 
      4 /* ARM DAP Controller (4bit IR) */
      5 #define DAP_IR_SIZE		4
      6 
      7 #define DAP_IR_ABORT		0x08
      8 #define DAP_IR_DPACC		0x0A
      9 #define DAP_IR_APACC		0x0B
     10 #define DAP_IR_IDCODE		0x0E
     11 #define DAP_IR_BYPASS		0x0F
     12 
     13 /* DPACC/APACC DR bits */
     14 #define XPACC_STATUS(n)		((n) & 0x3)
     15 #define XPACC_WAIT		0x1
     16 #define XPACC_OK		0x2
     17 #define XPACC_RD(a)		(0x1 | (((a) >> 1) & 6))
     18 #define XPACC_WR(a,v)		((((u64)(v)) << 3) | (0x0 | (((a) >> 1) & 6)))
     19 
     20 /* DP addresses */
     21 #define DPACC_RESERVED		0x0
     22 #define DPACC_CSW		0x4
     23 #define DPACC_SELECT		0x8
     24 #define DPACC_RDBUFF		0xC
     25 
     26 #define DPCSW_CSYSPWRUPACK	(1 << 31)
     27 #define DPCSW_CSYSPWRUPREQ	(1 << 30)
     28 #define DPCSW_CDBGPWRUPACK	(1 << 29)
     29 #define DPCSW_CDBGPWRUPREQ	(1 << 28)
     30 #define DPCSW_CDBGRSTACK	(1 << 27)
     31 #define DPCSW_CDBGRSTREQ	(1 << 26)
     32 #define DPCSW_TRNCNT(n)		(((n) & 0x3FF) << 12)
     33 #define DPCSW_MASKLANE(n)	(((n) & 0xF) << 8) // pushed verify or compare
     34 #define DPCSW_WDATAERR		(1 << 7) // reserved on jtag
     35 #define DPCSW_READOK		(1 << 6) // reserved on jtag
     36 #define DPCSW_STICKYERR		(1 << 5)
     37 #define DPCSW_STICKYCMP		(1 << 4)
     38 #define DPCSW_TRNMODE_NORMAL	(0 << 2)
     39 #define DPCSW_TRNMODE_PUSH_VRFY	(1 << 2)
     40 #define DPCSW_TRNMODE_PUSH_CMP	(2 << 2)
     41 #define DPCSW_STICKYORUN	(1 << 1)
     42 #define DPCSW_ORUNDETECT	(1 << 0)
     43 
     44 #define DPSEL_APSEL(n)		(((n) & 0xFF) << 24)
     45 #define DPSEL_APBANKSEL(a)	((a) & 0xF0)
     46 #define DPSEL_CTRLSEL		(1 << 0) // reserved on jtag
     47 
     48 /* Reading RDBUFF returns 0, has no side effects */
     49 /* Can be used to obtain final read result and ack values at end of seq */
     50 
     51 /* AP addresses */
     52 #define APACC_CSW		0x00
     53 #define APACC_TAR		0x04
     54 #define APACC_DRW		0x0C
     55 #define APACC_BD0		0x10
     56 #define APACC_BD1		0x14
     57 #define APACC_BD2		0x18
     58 #define APACC_BD3		0x1C
     59 #define APACC_CFG		0xF4
     60 #define APACC_BASE		0xF8
     61 #define APACC_IDR		0xFC
     62 
     63 #define APCSW_DBGSWEN		(1 << 31)
     64 #define APCSW_PROT_MASK		0x7F000000
     65 #define APCSW_SPIDEN		(1 << 23) // ro
     66 #define APCSW_TRBUSY		(1 << 7) // ro
     67 #define APCSW_DEVICEEN		(1 << 6) // ro
     68 #define APCSW_INCR_NONE		(0 << 4)
     69 #define APCSW_INCR_SINGLE	(1 << 4)
     70 #define APCSW_INCR_PACKED	(2 << 4) // may not be supported
     71 #define APCSW_SIZE8		(0 << 0) // may not be supported
     72 #define APCSW_SIZE16		(1 << 0) // may not be supported
     73 #define APCSW_SIZE32		(2 << 0) 
     74 
     75 #endif