ne2000.h (7977B)
1 /* $Id: //depot/blt/srv/ne2000/ne2000.h#2 $ 2 ** 3 ** Copyright 1998 Brian J. Swetland 4 ** All rights reserved. 5 ** 6 ** Redistribution and use in source and binary forms, with or without 7 ** modification, are permitted provided that the following conditions 8 ** are met: 9 ** 1. Redistributions of source code must retain the above copyright 10 ** notice, this list of conditions, and the following disclaimer. 11 ** 2. Redistributions in binary form must reproduce the above copyright 12 ** notice, this list of conditions, and the following disclaimer in the 13 ** documentation and/or other materials provided with the distribution. 14 ** 3. The name of the author may not be used to endorse or promote products 15 ** derived from this software without specific prior written permission. 16 ** 17 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 #ifndef __NE2000_SHARED_CODE_BASE 29 #define __NE2000_SHARED_CODE_BASE 30 typedef unsigned int uint; 31 typedef struct snic snic; 32 typedef struct nic_stat nic_stat; 33 typedef struct buffer_header buffer_header; 34 typedef struct packet_data packet_data; 35 typedef struct packet_buffer packet_buffer; 36 typedef struct nic_error_stat nic_error_stat; 37 38 /* internal implementation procedures */ 39 int nic_probe(int addr); 40 int nic_dump_prom(snic *nic, unsigned char *prom); 41 void nic_overrun(snic *nic); 42 void nic_tx(snic *nic); 43 void nic_tx_err(snic *nic); 44 void nic_rx(snic *nic); 45 void nic_counters(snic *nic); 46 void nic_get_header(snic *nic, uint page, buffer_header *header); 47 int nic_send(snic *nic, uint buf); 48 void nic_block_input(snic *nic, unsigned char *buf, uint len, uint offset); 49 void nic_block_output(snic *nic, packet_buffer *pkt); 50 51 #define PSTART 0x20 /* if NE2000 is byte length */ 52 #define PSTOP 0x40 53 #define PSTARTW 0x40 /* if NE2000 is wordlength */ 54 #define PSTOPW 0x80 55 #define MAX_LOAD 12 /* maximum services per IRQ request*/ 56 #define MAX_RX 10 /* maximum packets recieve per call*/ 57 #define MIN_LENGTH 60 /* minimum length for packet data */ 58 #define MAX_LENGTH 1500 /* maximum length for packet data area */ 59 #define TIMEOUT_DMAMATCH 40 /* for nic_block_input() */ 60 #define TIMEOUT_TX 40 61 62 /* DP8390 NIC Registers*/ 63 #define COMMAND 0x00 64 #define STATUS COMMAND+0 65 #define PHYSICAL COMMAND+1 /* page 1 */ 66 #define MULTICAST COMMAND+8 /* page 1 */ 67 #define PAGESTART COMMAND+1 /* page 0 */ 68 #define PAGESTOP COMMAND+2 69 #define BOUNDARY COMMAND+3 70 #define TRANSMITSTATUS COMMAND+4 71 #define TRANSMITPAGE COMMAND+4 72 #define TRANSMITBYTECOUNT0 COMMAND+5 73 #define NCR COMMAND+5 74 #define TRANSMITBYTECOUNT1 COMMAND+6 75 #define INTERRUPTSTATUS COMMAND+7 76 #define CURRENT COMMAND+7 /* page 1 */ 77 #define REMOTESTARTADDRESS0 COMMAND+8 78 #define CRDMA0 COMMAND+8 79 #define REMOTESTARTADDRESS1 COMMAND+9 80 #define CRDMA1 COMMAND+9 81 #define REMOTEBYTECOUNT0 COMMAND+10 /* how many bytes we will */ 82 #define REMOTEBYTECOUNT1 COMMAND+11 /* read through remote DMA->IO */ 83 #define RECEIVESTATUS COMMAND+12 84 #define RECEIVECONFIGURATION COMMAND+12 85 #define TRANSMITCONFIGURATION COMMAND+13 86 #define FAE_TALLY COMMAND+13 /* page 0 */ 87 #define DATACONFIGURATION COMMAND+14 88 #define CRC_TALLY COMMAND+14 89 #define INTERRUPTMASK COMMAND+15 90 #define MISS_PKT_TALLY COMMAND+15 91 92 /* NE2000 specific implementation registers */ 93 #define NE_RESET 0x1f /* Reset */ 94 #define NE_DATA 0x10 /* Data port (use for PROM) */ 95 96 #define PAR0 COMMAND+1 97 #define PAR1 COMMAND+2 98 #define PAR2 COMMAND+3 99 #define PAR3 COMMAND+4 100 #define PAR4 COMMAND+5 101 #define PAR5 COMMAND+6 102 103 /* NIC Commands */ 104 #define NIC_STOP 0x01 /* STOP */ 105 #define NIC_START 0x02 /* START */ 106 #define NIC_PAGE0 0x00 107 #define NIC_PAGE1 0x40 108 #define NIC_PAGE2 0x80 109 #define NIC_TRANSMIT 0x04 /* Transmit a frame */ 110 #define NIC_REM_READ 0x08 /* Remote Read */ 111 #define NIC_REM_WRITE 0x10 /* Remote Write */ 112 #define NIC_DMA_DISABLE 0x20 /* Disable DMA */ 113 114 /* Data Configuration Register */ 115 #define DCR_WTS 0x01 /* Word Transfer Select (0=byte, 1=word) */ 116 #define DCR_BOS 0x02 /* Byte Order Select (0=big-endian) */ 117 #define DCR_LAS 0x04 /* Long Address Select (0=dual 16-bit DMA) */ 118 #define DCR_LS 0x08 /* Loopback Select (0=loopback) */ 119 #define DCR_AR 0x10 /* Auto Initialize Remote */ 120 #define DCR_FT 0x60 /* (FT0 & FT1) FIFO Threshhold (see datasheet) */ 121 /*#define DCR_DEFAULT 0x58 Standard value for the DCR register */ 122 #define DCR_DEFAULT 0x48 /* don't use Automatic send packet */ 123 #define DCR_DEFAULT_WORD 0x49 /* defuault with wold length transfer */ 124 125 /* Recieve Configure Register */ 126 #define RCR_SEP 0x01 /* Save Errored Packets */ 127 #define RCR_AR 0x02 /* Accept Runt Packets */ 128 #define RCR_AB 0x04 /* Accept Broadcast */ 129 #define RCR_AM 0x08 /* Accept Multicast */ 130 #define RCR_PRO 0x10 /* Promiscuous Physical */ 131 #define RCR_MON 0x20 /* Monitor Mode */ 132 /*#define RCR_DEFAULT 0x00 Standard value for the RCR register */ 133 #define RCR_DEFAULT 0x0c /* Accept Broadcast/Multicast Packets */ 134 135 /* Recieve Status Register */ 136 /* note, this is also stored in the status byte in the buffer header. */ 137 /* That's the 4 byte entry in the local buffer, not the packet header. */ 138 #define RSR_PRX 0x01 /* Pakcet Received Intact */ 139 #define RSR_CRC 0x02 /* CRC Error */ 140 #define RSR_FAE 0x04 /* Frame Alignment Error */ 141 #define RSR_FO 0x08 /* FIFO Overrun */ 142 #define RSR_MPA 0x10 /* Missed Packet */ 143 #define RSR_PHY 0x20 /* Physical/Multicast Address (0=physical) */ 144 #define RSR_DIS 0x40 /* Receiver Disabled */ 145 #define RSR_DFR 0x80 /* Deferring */ 146 147 /* Transmit Configure Register */ 148 #define TCR_CRC 0x01 /* Inhibit CRC (0=CRC active) */ 149 #define TCR_LB 0x06 /* (LB0 & LB1) Encoded Loopback Control */ 150 #define TCR_ATD 0x08 /* Auto Transmit Disable (0=normal) */ 151 #define TCR_OFST 0x10 /* Collision Offset Enable (1=low priority) */ 152 #define TCR_DEFAULT 0x00 /* Standard value for the TCR register */ 153 #define TCR_INTERNAL_LOOPBACK 0x02 /* Internal loopback configuration */ 154 155 /* Transmit Status Register */ 156 #define TSR_PTX 0x01 /* Packet Transmitted */ 157 #define TSR_ND 0x02 /* Non-Deferral (Documented???) */ 158 #define TSR_COL 0x04 /* Transmit Collided */ 159 #define TSR_ABT 0x08 /* Transmit Aborted */ 160 #define TSR_CRS 0x10 /* Carrier Sense Lost */ 161 #define TSR_FU 0x20 /* FIFO Underrun */ 162 #define TSR_CDH 0x40 /* CD Heartbeat */ 163 #define TSR_OWC 0x80 /* Oout of Window Collision */ 164 165 /* Interrupt Status Register */ 166 #define ISR_PRX 0x01 /* Packet Received */ 167 #define ISR_PTX 0x02 /* Packet Transmitted */ 168 #define ISR_RXE 0x04 /* Receive Error */ 169 #define ISR_TXE 0x08 /* Transmit Error */ 170 #define ISR_OVW 0x10 /* Overwrite Warning */ 171 #define ISR_CNT 0x20 /* Counter Overflow */ 172 #define ISR_RDC 0x40 /* Remote DMA Complete */ 173 #define ISR_RST 0x80 /* Reset Status */ 174 #define ISR_DEFAULT 0x00 /* Standard value for the ISR register */ 175 #define ISR_ALL 0x3f /* The services that we handle in the isr */ 176 177 /* Interrupt Mask Register */ 178 #define IMR_PRXE 0x01 /* Packet Received Interrupt Enable */ 179 #define IMR_PTXE 0x02 /* Packet Transmitted Interrupt Enable */ 180 #define IMR_RXEE 0x04 /* Receive Error Interrupt Enable */ 181 #define IMR_TXEE 0x08 /* Transmit Error Interrupt Enable */ 182 #define IMR_OVWE 0x10 /* Overwrite Warning Interrupt Enable */ 183 #define IMR_CNTE 0x20 /* Counter Overflow Interrupt Enable */ 184 #define IMR_RDCE 0x40 /* DMA Complete Interrupt Enable */ 185 #define IMR_DEFAULT 0x3f /* CNTE | OVWE | TXEE | RXEE | PTXE | PRXE */ 186 187 #endif