os-workshop

same materials and sample source for RV32 OS projects
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traps-entry.S (2127B)


      1 // Copyright 2022, Brian Swetland <swetland@frotz.net>
      2 // Licensed under the Apache License, Version 2.0
      3 
      4 #include <hw/riscv.h>
      5 
      6 .globl svc_exception_entry
      7 svc_exception_entry:
      8 	// swap active sp with value in SSCRATCH (svc stack)
      9 	// interupts have been disabled on exception entry
     10 	csrrw sp, CSR_SSCRATCH, sp
     11 
     12 	// todo: beqz svc_nested_irq_entry
     13 
     14 	// save previous registers to stack
     15 	addi sp, sp, - (32 * 4)
     16 	sw x1, 0x04(sp)
     17 	sw x3, 0x0C(sp)
     18 	sw x4, 0x10(sp)
     19 	sw x5, 0x14(sp)
     20 	sw x6, 0x18(sp)
     21 	sw x7, 0x1C(sp)
     22 	sw x8, 0x20(sp)
     23 	sw x9, 0x24(sp)
     24 	sw x10, 0x28(sp)
     25 	sw x11, 0x2C(sp)
     26 	sw x12, 0x30(sp)
     27 	sw x13, 0x34(sp)
     28 	sw x14, 0x38(sp)
     29 	sw x15, 0x3C(sp)
     30 	sw x16, 0x40(sp)
     31 	sw x17, 0x44(sp)
     32 	sw x18, 0x48(sp)
     33 	sw x19, 0x4C(sp)
     34 	sw x20, 0x50(sp)
     35 	sw x21, 0x54(sp)
     36 	sw x22, 0x58(sp)
     37 	sw x23, 0x5C(sp)
     38 	sw x24, 0x60(sp)
     39 	sw x25, 0x64(sp)
     40 	sw x26, 0x68(sp)
     41 	sw x27, 0x6C(sp)
     42 	sw x28, 0x70(sp)
     43 	sw x29, 0x74(sp)
     44 	sw x30, 0x78(sp)
     45 	sw x31, 0x7C(sp)
     46 
     47 	// save user pc (hw stashed it in SEPC)
     48 	csrr t0, CSR_SEPC
     49 	sw t0, 0x00(sp)
     50 
     51 	// save user sp (we stashed it in SSCRATCH)
     52 	// and stick 0 in CSR_SSCRATCH so we can detect nested irqs
     53 	csrrw t0, CSR_SSCRATCH, x0
     54 	sw t0, 0x08(sp)
     55 
     56 	mv a0, sp
     57 	jal svc_exception_handler
     58 
     59 	// save svc sp in SSCRATCH for next interrupt
     60 	addi t0, sp, (32 * 4)
     61 	csrw CSR_SSCRATCH, t0
     62 
     63 	// user pc goes into SEPC for sret
     64 	lw t0, 0x00(sp)
     65 	csrw CSR_SEPC, t0
     66 
     67 	lw x1, 0x04(sp)
     68 	lw x3, 0x0C(sp)
     69 	lw x4, 0x10(sp)
     70 	lw x5, 0x14(sp)
     71 	lw x6, 0x18(sp)
     72 	lw x7, 0x1C(sp)
     73 	lw x8, 0x20(sp)
     74 	lw x9, 0x24(sp)
     75 	lw x10, 0x28(sp)
     76 	lw x11, 0x2C(sp)
     77 	lw x12, 0x30(sp)
     78 	lw x13, 0x34(sp)
     79 	lw x14, 0x38(sp)
     80 	lw x15, 0x3C(sp)
     81 	lw x16, 0x40(sp)
     82 	lw x17, 0x44(sp)
     83 	lw x18, 0x48(sp)
     84 	lw x19, 0x4C(sp)
     85 	lw x20, 0x50(sp)
     86 	lw x21, 0x54(sp)
     87 	lw x22, 0x58(sp)
     88 	lw x23, 0x5C(sp)
     89 	lw x24, 0x60(sp)
     90 	lw x25, 0x64(sp)
     91 	lw x26, 0x68(sp)
     92 	lw x27, 0x6C(sp)
     93 	lw x28, 0x70(sp)
     94 	lw x29, 0x74(sp)
     95 	lw x30, 0x78(sp)
     96 	lw x31, 0x7C(sp)
     97 
     98 	// grab user sp back off of the svc stack
     99 	lw sp, 0x08(sp)
    100 
    101 	// save previous pc (hw stashed it in MEPC)
    102 	sret
    103 
    104 .globl enter_mode_u
    105 enter_mode_u: // (a0, a1, user_pc, user_sp)
    106 	csrw CSR_SEPC, a2
    107 	mv sp, a3
    108 	sret
    109