riscv

an RV32I simulator and related experiments
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riscv.h (4210B)


      1 // Copyright 2019, Brian Swetland <swetland@frotz.net>
      2 // Licensed under the Apache License, Version 2.0.
      3 
      4 #pragma once
      5 
      6 #include <stdint.h>
      7 
      8 // extract instruction fields
      9 static inline uint32_t get_oc(uint32_t ins) {
     10 	return ins & 0x7f;
     11 }
     12 static inline uint32_t get_rd(uint32_t ins) {
     13 	return (ins >> 7) & 0x1f;
     14 }
     15 static inline uint32_t get_r1(uint32_t ins) {
     16 	return (ins >> 15) & 0x1f;
     17 }
     18 static inline uint32_t get_r2(uint32_t ins) {
     19 	return (ins >> 20) & 0x1f;
     20 }
     21 static inline uint32_t get_ii(uint32_t ins) {
     22 	return ((int32_t)ins) >> 20;
     23 }
     24 static inline uint32_t get_is(uint32_t ins) {
     25 	return ((((int32_t)ins) >> 20) & 0xffffffe0) | ((ins >> 7) & 0x1f);
     26 }
     27 static inline uint32_t get_ib(uint32_t ins) {
     28 	return ((ins >> 7) & 0x1e) |
     29 		((ins >> 20) & 0x7e0) |
     30 		((ins << 4) & 0x800) |
     31 		(((int32_t)(ins & 0x80000000)) >> 19);
     32 }
     33 static inline uint32_t get_iu(uint32_t ins) {
     34 	return ins & 0xFFFFF000;
     35 }
     36 static inline uint32_t get_ij(uint32_t ins) {
     37 	return (((int32_t)(ins & 0x80000000)) >> 11) |
     38 		(ins & 0xFF000) |
     39 		((ins >> 9) & 0x800) |
     40 		((ins >> 20) & 0x7fe);
     41 }
     42 static inline uint32_t get_fn3(uint32_t ins) {
     43 	return (ins >> 12) & 7;
     44 }
     45 static inline uint32_t get_fn7(uint32_t ins) {
     46 	return ins >> 25;
     47 }
     48 static inline uint32_t get_ic(uint32_t ins) {
     49 	return (ins >> 15) & 0x1F;
     50 }
     51 static inline uint32_t get_iC(uint32_t ins) {
     52 	return ins >> 20;
     53 }
     54 
     55 
     56 // opcode constants (6:0)
     57 #define OC_LOAD     0b0000011
     58 #define OC_CUSTOM_0 0b0001011
     59 #define OC_MISC_MEM 0b0001111
     60 #define OC_OP_IMM   0b0010011
     61 #define OC_AUIPC    0b0010111
     62 #define OC_STORE    0b0100011
     63 #define OC_OP       0b0110011
     64 #define OC_LUI      0b0110111
     65 #define OC_BRANCH   0b1100011
     66 #define OC_JALR     0b1100111
     67 #define OC_JAL      0b1101111
     68 #define OC_SYSTEM   0b1110011
     69 
     70 // further discrimination of OC_OP_IMM (14:12)
     71 #define F3_ADDI  0b000
     72 #define F3_SLLI  0b001 // 0b0000000
     73 #define F3_SLTI  0b010
     74 #define F3_SLTIU 0b011
     75 #define F3_XORI  0b100
     76 #define F3_SRLI  0b101 // 0b0000000
     77 #define F3_SRAI  0b101 // 0b0100000
     78 #define F3_ORI   0b110
     79 #define F3_ANDI  0b111
     80 
     81 // further discrimination of OC_OP_LOAD (14:12)
     82 #define F3_LB  0b000
     83 #define F3_LH  0b001
     84 #define F3_LW  0b010
     85 #define F3_LBU 0b100
     86 #define F3_LHU 0b101
     87 
     88 // further discrimination of OC_OP_STORE (14:12)
     89 #define F3_SB 0b000
     90 #define F3_SH 0b001
     91 #define F3_SW 0b010
     92 
     93 // further discrimination of OC_OP (14:12) (fn7==0)
     94 #define F3_ADD  0b000
     95 #define F3_SLL  0b001
     96 #define F3_SLT  0b010
     97 #define F3_SLTU 0b011
     98 #define F3_XOR  0b100
     99 #define F3_SRL  0b101
    100 #define F3_OR   0b110
    101 #define F3_AND  0b111
    102 
    103 // OC_OP (14:12) (fn7==0b0100000)
    104 #define F3_SUB  0b000
    105 #define F3_SRA  0b101
    106 
    107 // OC_OP (14:12) (fn7==0b0000001)
    108 #define F3_MUL    0b000
    109 #define F3_MULH   0b001
    110 #define F3_MULHSU 0b010
    111 #define F3_MULHU  0b011
    112 #define F3_DIV    0b100
    113 #define F3_DIVU   0b101
    114 #define F3_REM    0b110
    115 #define F3_REMU   0b111
    116 
    117 // further discrimination of OC_BRANCH
    118 #define F3_BEQ  0b000
    119 #define F3_BNE  0b001
    120 #define F3_BLT  0b100
    121 #define F3_BGE  0b101
    122 #define F3_BLTU 0b110
    123 #define F3_BGEU 0b111
    124 
    125 // further discrimination of OC_SYSTEM (13:12)
    126 #define F3_CSRRW 0b01
    127 #define F3_CSRRS 0b10
    128 #define F3_CSRRC 0b11
    129 
    130 // further discrimination of OC_MISC_MEM (14:12)
    131 #define F3_FENCE   0b000
    132 #define F3_FENCE_I 0b001
    133 
    134 // CSR values
    135 #define CSR_MVENDORID   0xF11
    136 #define CSR_MARCHID     0xF12
    137 #define CSR_MIMPID      0xF13
    138 #define CSR_MHARTID     0xF14
    139 
    140 #define CSR_MSTATUS     0x300
    141 #define CSR_MISA        0x301
    142 #define CSR_MEDELEG     0x302
    143 #define CSR_MIDELEG     0x303
    144 #define CSR_MIE         0x304
    145 #define CSR_MTVEC       0x305
    146 #define CSR_MCOUNTEREN  0x306
    147 
    148 #define CSR_MSCRATCH    0x340
    149 #define CSR_MEPC        0x341
    150 #define CSR_MCAUSE      0x342
    151 #define CSR_MTVAL       0x343
    152 #define CSR_MIP         0x344
    153 
    154 // exception codes
    155 #define EC_I_ALIGN       0
    156 #define EC_I_ACCESS      1
    157 #define EC_I_ILLEGAL     2
    158 #define EC_BREAKPOINT    3
    159 #define EC_L_ALIGN       4
    160 #define EC_L_ACCESS      5
    161 #define EC_S_ALIGN       6
    162 #define EC_S_ACCESS      7
    163 #define EC_ECALL_FROM_U  8
    164 #define EC_ECALL_FROM_S  9
    165 #define EC_ECALL_FROM_M  11
    166 #define EC_I_PAGEFAULT   12
    167 #define EC_L_PAGEFAULT   13
    168 #define EC_S_PAGEFAULT   15
    169 
    170 void rvdis(uint32_t pc, uint32_t ins, char *out);
    171 const char* rvregname(uint32_t n);
    172