riscv

an RV32I simulator and related experiments
git clone http://frotz.net/git/riscv.git
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simple.ld (178B)

      1 
      2 MEMORY {
      3 	mem : ORIGIN = 0x80000000, LENGTH = 0x00010000
      4 }
      5 
      6 SECTIONS {
      7 	.memory : {
      8 		. = 0x00000000;
      9 		start*(.text);
     10 		*(.text);
     11 		*(*);
     12 		end = .;
     13 		. = ALIGN(4);
     14 	} > mem
     15 }