riscv

an RV32I simulator and related experiments
git clone http://frotz.net/git/riscv.git
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model_test.h (802B)

      1 #ifndef _MODEL_TEST_H
      2 #define _MODEL_TEST_H
      3 
      4 // #include "riscv_test.h"
      5 
      6 #define RVMODEL_RV32M
      7 
      8 #define RVMODEL_BOOT .globl _start; _start:
      9 
     10 #define RVMODEL_DATA_BEGIN \
     11 	.align 4; .globl begin_signature; begin_signature:
     12 #define RVMODEL_DATA_END \
     13 	.align 4; .globl end_signature; end_signature:
     14 
     15 #define RVMODEL_HALT .long 0x0000000b;
     16 #define RVMODEL_CODE_BEGIN
     17 #define RVMODEL_CODE_END
     18 // .globl _start; \
     19 //_start: \
     20 //begin_testcode: \
     21 
     22 #define RVMODEL_IO_INIT
     23 #define RVMODEL_IO_WRITE_STR(_SP, _STR)
     24 #define RVMODEL_IO_CHECK()
     25 #define RVMODEL_IO_ASSERT_GPR_EQ(_SP, _R, _I)
     26 #define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I)
     27 #define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)
     28 
     29 #define RVMODEL_SET_MSW_INT
     30 #define RVMODEL_CLEAR_MSW_INT
     31 #define RVMODEL_CLEAR_MTIMER_INT
     32 #define RVMODEL_CLEAR_MEXT_INT
     33 
     34 #endif