README.md (741B)
1 2 # softrisc32 3 4 A "toy" 32bit RISC architecture inspired by RISC-V. 5 6 It's designed to be a very similar "shape" to the RV32I ISA, 7 but is tuned for maximum friendliness toward simple emulators, 8 toolchains, etc rather than tweaked for most optimal hardware 9 implementation, expandability, etc. 10 11 In particular: 12 - it only concerns itself with a 32bit ISA 13 - it optimizes instruction encoding for simplicity of software 14 implementation and at-a-glace comprehensibility by humans 15 - it attempts to allow for a trivial conversion of generated 16 code or code generators to RV32I, provided the RV32I immediate 17 size constraints are used instead of the slightly more generous SR32 ones. 18 19 Instruction Set Summary and Encoding: [softrisc32.txt](softrisc32.txt)