softrisc32.txt (2410B)
1 2 softrisc32 emulator-friendly 32bit integer ISA 3 ============================================== 4 5 3 2 1 6 10987654321098765432109876543210 7 -------------------------------- 8 I iiiiiiiiiiiiiiiiaaaaattttt00oooo i16 9 R 00000000nnnbbbbbaaaaattttt01oooo i0 10 L iiiiiiiiiiiiiiiiaaaaattttt100ooo i16 11 S iiiiiiiiiiiiiiiiaaaaabbbbb101ooo i16 12 B iiiiiiiiiiiiiiiiaaaaabbbbb110ooo i16 13 J iiiiiiiiiiiiiiiiiiiiittttt111ooo i21 14 15 I(mmediate)/R(egister) 16 ---------------------- 17 0 addi / add Rt = Ra + b 18 1 subi / sub Rt = Ra - b 19 2 andi / and Rt = Ra & b 20 3 ori / or Rt = Ra | b 21 4 xori / xor Rt = Ra ^ b 22 5 slli / sll Rt = Ra << (b & 31) 23 6 srli / srl Rt = Ra >> (b & 31) (unsigned) 24 7 srai / sra Rt = Ra >> (b & 31) (signed) 25 8 slti / slt Rt = (Ra < b) ? 1 : 0 26 9 sltui / sltu Rt = (Ra < b) ? 1 : 0 (unsigned) 27 a muli / mul Rt = Ra mulop* b 28 b divi / div Rt = Ra divop* b 29 c - 30 d - 31 e - 32 f - jalr Rt = pc + 4, pc = Ra + b 33 * mul/divop (n) is 0 for imm variants 34 35 B(ranch) 36 -------- 37 0 beq Ra == Rb ? pc = pc + 4 + i 38 1 bne Ra != Rb ? pc = pc + 4 + i 39 2 blt Ra < Rb ? pc = pc + 4 + i 40 3 bltu Ra < Rb ? pc = pc + 4 + i (unsigned) 41 4 bge Ra >= Rb ? pc = pc + 4 + i 42 5 bgeu Ra >= Rb ? pc = pc + 4 + i (unsigned) 43 6 - 44 7 - 45 46 L(oad) 47 ------ 48 0 ldw Rt = (u32*)[Ra + i] 49 1 ldh Rt = (u16*)[Ra + i] (sign extended) 50 2 ldb Rt = (u8*)[Ra + i] (sign extended) 51 3 ldx Rt = io_read(Ra + i) 52 4 lui Rt = i << 16 53 5 ldhu Rt = (u16*)[Ra + i] 54 6 ldbu Rt = (u8*)[Ra + i] 55 7 auipc Rt = pc + 4 + (i << 16) 56 57 S(store) 58 -------- 59 0 stw (u32*)[Ra + i] = Rb 60 1 sth (u16*)[Ra + i] = Rb 61 2 stb (u8*)[Ra + i] = Rb 62 3 stx io_write(Ra + i, Rb) 63 4 - 64 5 - 65 6 - 66 7 - 67 68 J(ump) 69 ------ 70 0 jal Rt = pc + 4, pc = pc + 4 + i 71 1 syscall XPC = pc + 4, pc = SYSCALL_VECTOR (Rt = 0, i = sysno) 72 2 break XPC = pc + 4, pc = BREAK_VECTOR (Rt = 0, i = 0) 73 3 sysret pc = XPC (Rt = 0, i = 0) 74 4 - 75 5 - 76 6 - 77 7 - 78 79 undefined XPC = pc + 4, pc = UNDEFINED_VECTOR 80 81 - in I/R encodings, b is Rb for R, and i16 for I 82 - integer constants are arithmetic right shifted by 32 - width. 83 - reads from r0 always return 0 84 - writes to r0 have no effect 85 - writes to pc force the low two bits to 0 86 - 32 bit loads and stores force the two low address bits to 0 87 - 16 bit loads and stores force the low address bit to 0 88