arm-debug.h (4839B)
1 // Copyright 2023, Brian Swetland <swetland@frotz.net> 2 // Licensed under the Apache License, Version 2.0. 3 4 // see: ARM IHI 0031G 5 // Arm Debug Interface Architecture Specification 6 // ADIv5.0 to ADIv5.2 7 8 #pragma once 9 10 // high nybble is banksel 11 #define DP_DPIDR 0x00 // RO Debug Port ID 12 #define DP_ABORT 0x00 // WO 13 #define DP_CS 0x04 // RW CTRL/STAT 14 #define DP_DLCR 0x14 // RW Data Link Control 15 #define DP_TARGETID 0x24 // RO v2 16 #define DP_DLPIDR 0x34 // RO v2 Data Link Protocol ID 17 #define DP_EVENTSTAT 0x44 // RO v2 18 #define DP_SELECT 0x08 // WO 19 #define DP_RESEND 0x08 // RO v2 Return last AP or RDBUFF read data 20 #define DP_RDBUFF 0x0C // RO 21 #define DP_TARGETSEL 0x0C // WO v2 22 23 #define DP_ABORT_DAPABORT 0x01U // Abort Current AP Txn 24 #define DP_ABORT_STKCMPCLR 0x02U // clear CS.STICKYCMP 25 #define DP_ABORT_STKERRCLR 0x04U // clear CS.STICKYERR 26 #define DP_ABORT_WDERRCLR 0x08U // clear CS.WDATAERR 27 #define DP_ABORT_ORUNERRCLR 0x10U // clear CS.STICKYORUN 28 #define DP_ABORT_ALLCLR 0x1EU 29 30 #define DP_CS_ORUNDETECT 0x00000001U // RW 31 #define DP_CS_STICKYORUN 0x00000002U // RO/WI 32 #define DP_CS_MODE_MASK 0x0000000CU // RW 33 #define DP_CS_MODE_NORMAL 0x00000000U 34 #define DP_CS_MODE_PUSHED_VERIFY 0x00000004U 35 #define DP_CS_MODE_PUSHED_COMPARE 0x00000008U 36 #define DP_CS_MODE_RESERVED 0x0000000CU 37 #define DP_CS_STICKYCMP 0x00000010U // RO/WI for pushed ops 38 #define DP_CS_STICKYERR 0x00000020U // RO/WI error occurred in AP txn 39 #define DP_CS_READOK 0x00000040U // RO/WI last AP or RDBUFF RD was OK 40 #define DP_CS_WDATAERR 0x00000080U // RO/WI 41 #define DP_CS_MASKLANE(n) (((n) & 0xFU) << 8) // RW 42 #define DP_CS_TRNCNT(n) (((n) & 0xFFFU) << 12) 43 #define DP_CS_CDBGRSTREQ 0x04000000U // RW or RAZ/WI 44 #define DP_CS_CDBGRSTACK 0x08000000U // RO 45 #define DP_CS_CDBGPWRUPREQ 0x10000000U // RW 46 #define DP_CS_CDBGPWRUPACK 0x20000000U // RO 47 #define DP_CS_CSYSPWRUPREQ 0x40000000U // RW 48 #define DP_CS_CSYSPWRUPACK 0x80000000U // RO 49 50 #define DP_DLCR_TURNROUND_MASK 0x00000300U 51 #define DP_DLCR_TURNROUND_1 0x00000000U 52 #define DP_DLCR_TURNROUND_2 0x00000100U 53 #define DP_DLCR_TURNROUND_3 0x00000200U 54 #define DP_DLCR_TURNROUND_4 0x00000300U 55 #define DP_DLCR_MUST_BE_ONE 0x00000040U 56 57 #define DP_EVENTSTAT_EA 0x000000001U 58 59 #define DP_SELECT_DPBANK(n) ((n) & 0xFU) 60 #define DP_SELECT_APBANK(n) (((n) & 0xFU) << 4) 61 #define DP_SELECT_AP(n) (((n) & 0xFFU) << 24) 62 63 // Memory AP 64 65 #define MAP_CSW 0x00 // RW Control/Status Word 66 #define MAP_TAR 0x04 // RW Transfer Address Reg 67 #define MAP_TAR_H 0x08 // RW Transfer Address Reg (HI) 68 #define MAP_DRW 0x0C // RW Data Read/Write 69 #define MAP_BD0 0x10 // RW Banked Data Reg 0 70 #define MAP_BD1 0x14 71 #define MAP_BD2 0x18 72 #define MAP_BD3 0x1C 73 #define MAP_MBT 0x20 // ?? Memory Barrier Transfer 74 #define MAP_T0TR 0x30 // RW Tag 0 Transfer Reg 75 #define MAP_CFG1 0xE0 // RO Config Register 1 76 #define MAP_BASE_H 0xF0 // RO Debug Base Addr (HI) 77 #define MAP_CFG 0xF4 // RO Config Register 0 78 #define MAP_BASE 0xF8 // RO Debug Base Addr 79 #define MAP_IDR 0xFC // RO Identification Reg 80 81 #define MAP_CFG_LD 0x04 // Large Data Extension (>32bit) 82 #define MAP_CFG_LA 0x02 // Large Addr Extension (>32bit) 83 #define MAP_CFG_BE 0x01 // Big Endian (obsolete in 5.2) 84 85 #define MAP_CSW_SZ_MASK 0x00000007U 86 #define MAP_CSW_SZ_8 0x00000000U 87 #define MAP_CSW_SZ_16 0x00000001U 88 #define MAP_CSW_SZ_32 0x00000002U // always supported 89 #define MAP_CSW_SZ_64 0x00000003U 90 #define MAP_CSW_SZ_128 0x00000004U 91 #define MAP_CSW_SZ_256 0x00000005U 92 #define MAP_CSW_INC_MASK 0x00000030U 93 #define MAP_CSW_INC_OFF 0x00000000U 94 #define MAP_CSW_INC_SINGLE 0x00000010U 95 #define MAP_CSW_INC_PACKED 0x00000020U 96 #define MAP_CSW_DEVICE_EN 0x00000040U // Enable MEM AP 97 #define MAP_CSW_BUSY 0x00000080U // Transfer In Progress 98 #define MAP_CSW_MODE_MASK 0x00000F00U 99 #define MAP_CSW_MODE_BASIC 0x00000000U 100 #define MAP_CSW_MODE_BARRIER 0x00000100U 101 #define MAP_CSW_TYPE_MASK 0x00007000U 102 #define MAP_CSW_MTE 0x00008000U 103 #define MAP_CSW_SEC_DBG_EN 0x00800000U // Secure Debug Enable 104 #define MAP_CSW_PROT_MASK 0x7F000000U 105 #define MAP_CSW_DBG_SW_EN 0x80000000U // Debug SW Access Enable 106 107 #define MAP_CSW_KEEP 0xFF00FF00U // preserve mode/type/prot fields 108 109 110 #define AHB_CSW_PROT_PRIV 0x02000000U 111 #define AHB_CSW_MASTER_DEBUG 0x20000000U