arm-v7-debug.h (4617B)
1 // Copyright 2023, Brian Swetland <swetland@frotz.net> 2 // Licensed under the Apache License, Version 2.0. 3 4 #pragma once 5 6 // see: ARM v7-M Architecture Reference, C1 7 // see: ARM v6-M Architecture Reference, C1 8 9 #define DHCSR 0xE000EDF0 // RW Debug Halting Control/Status 10 #define DCRSR 0xE000EDF4 // WO Debug Core Register Selector 11 #define DCRDR 0xE000EDF8 // RW Debug Core Register Data 12 #define DEMCR 0xE000EDFC // RW Debug Exception & Monitor Control 13 14 15 // lower 16 bits are RW and have various restrictions 16 // Enable Halting Debug 17 // - cannot be modified by software, only DAP 18 // - if changing from 0 to 1, C_MASKINTS must be written as 0 19 // - 0 after power on reset 20 #define DHCSR_C_DEBUGEN 0x00000001 21 22 // Halt the Processor 23 // - state unknown when C_DEBUGEN is 0 24 #define DHCSR_C_HALT 0x00000002 25 26 // Enable Single Step 27 // - state unknown when C_DEBUGEN is 0 28 #define DHCSR_C_STEP 0x00000004 29 30 // mask PendSV, SysTick, and external interrupts 31 // - if C_HALT is not 1, writes are unpredictable 32 // - if C_MASKINTS is modified C_HALT must be written as 1 33 // or results are unpredictable 34 #define DHCSR_C_MASKINTS 0x00000008 // mask PenSV, SysTick, and Ext IRQs 35 36 // (v7M) Allow imprecise debug entry 37 // - can force stalled load/stores to complete 38 // - unpredictable if C_DEBUGEN and C_HALT are not also set to 1 39 // - make memory subsystem unpredictable when set: 40 // debugger must reset processor before leaving debug 41 #define DHCSR_C_SNAPSTALL 0x00000020 // (v7M) allow imprecise debug entry 42 43 // magic value must be written to modify the above bits 44 #define DHCSR_DBGKEY 0xA05F0000 45 46 // upper 16 bits are RO 47 #define DHCSR_S_REGRDY 0x00010000 // 0 on write to DCRSR, 1 when xfer done 48 #define DHCSR_S_HALT 0x00020000 // 1 if cpu halted (in debug) 49 #define DHCSR_S_SLEEP 0x00040000 // 1 when cpu sleeping 50 #define DHCSR_S_LOCKUP 0x00080000 // 1 if cpu locked up (cleared on debug entry) 51 #define DHCSR_S_RETIRE_ST 0x01000000 // 1 if instruction retired since last read 52 #define DHCSR_S_RESET_ST 0x02000000 // 1 if cpu reset since last read 53 54 55 // bit 16 controls read vs write 56 #define DCRSR_RD 0x00000000 57 #define DCRSR_WR 0x00010000 58 #define DCRSR_ID_MASK 0x0000FFFF 59 60 // to write: write value to DCRDR 61 // write (regno | DCRSR_WR) to DCRSR 62 // poll DHCSR until S_REGRDY is 1 63 // 64 // to read: write (regno | DCRSR_RD) to DCRSR 65 // poll DHCSR until S_REGRDY is 1 66 // read value from DCRDR 67 68 // 0..15 R0..R12,SP,LR,DebugReturnAddr 69 // 16 xPSR 70 // 17 MSP 71 // 18 PSP 72 // 20 CONTROL | PRIMASK (v6M) 73 74 // 20 CONTROL | FAULTMASK | BASEPRI | PRIMASK (v7M) 75 // 33 FPSCR (v7M w/ FPU) 76 // 64..95 S0..S31 (v7M w/ FPU) 77 78 79 #define DEMCR_VC_CORERESET 0x00000001 // Halt on Reset Vector * 80 #define DEMCR_VC_MMERR 0x00000010 // Halt on MemManage exception 81 #define DEMCR_VC_NOCPERR 0x00000020 // Halt on UsageFault for coproc access 82 #define DEMCR_VC_CHKERR 0x00000040 // Halt on UsageFault for checking errors 83 #define DEMCR_VC_STATERR 0x00000080 // Halt on UsageFault for state errors 84 #define DEMCR_VC_BUSERR 0x00000100 // Halt on BusFault 85 #define DEMCR_VC_INTERR 0x00000200 // Halt on exception entry/return faults 86 #define DEMCR_VC_HARDERR 0x00000400 // Halt on HardFault * 87 #define DEMCR_MON_EN 0x00010000 88 #define DEMCR_MON_PEND 0x00020000 89 #define DEMCR_MON_STEP 0x00040000 90 #define DEMCR_MON_REQ 0x00080000 91 #define DEMCR_TRCENA 0x01000000 // Enable DWT and ITM * 92 // v6M only has *'d bits 93 94 95 #define FP_CTRL 0xE0002000 96 #define FP_REMAP 0xE0002004 97 #define FP_COMP(n) (0xE0002008 + 8*(n)) 98 99 #define FP_CTRL_REV_MASK 0xF0000000 100 #define FP_CTRL_REV_V1 0x00000000 101 #define FP_CTRL_REV_V2 0x10000000 102 #define FP_CTRL_CODE_H_MASK 0x00007000 103 #define FP_CTRL_CODE_H_SHIFT 8 104 #define FP_CTRL_LIT_MASK 0x00000F00 105 #define FP_CTRL_LIT_SHIFT 8 106 #define FP_CTRL_CODE_L_MASK 0x000000F0 107 #define FP_CTRL_CODE_L_SHIFT 4 108 #define FP_CTRL_KEY 0x00000002 109 #define FP_CTRL_ENABLE 0x00000001 110 111 #define FP_REMAP_RMPSPT 0x20000000 112 113 #define FP1_COMP_REMAP 0x00000000 // REMAP 114 #define FP1_COMP_BK_00 0x40000000 // break on 000:COMP:00 115 #define FP1_COMP_BK_10 0x80000000 // break on 000:COMP:10 116 #define FP1_COMP_BK_x0 0xC0000000 // break on 000:COMP:x0 117 #define FP1_COMP_EN 0x00000001 118 119 #define FP2_COMP_DISABLE 0x00000000 120 #define FP2_COMP_BP_EN 0x00000001 121 #define FP2_COMP_FP_EN 0x80000000 122 #define FP2_COMP_BP_MASK 0xFFFFFFFE // allowed BP addr bits 123 #define FP2_COMP_FP_MASK 0x1FFFFFFE // allowed FP addr bits 124 125 126