arm-v7-system-control.h (3221B)
1 // Copyright 2023, Brian Swetland <swetland@frotz.net> 2 // Licensed under the Apache License, Version 2.0. 3 4 #pragma once 5 6 // see: ARM v7-M Architecture Reference, B3.2 7 // see: ARM v6-M Architecture Reference, B3.2 8 9 #define CPUID 0xE000ED00 // RO CPUID Base * 10 #define ICSR 0xE000ED04 // RW Interrupt Control/State * 11 #define VTOR 0xE000ED08 // RW Vector Table Offset * 12 #define AIRCR 0xE000ED0C // RW App Interrupt/Reset Control * 13 #define SCR 0xE000ED10 // RW System Control Register * 14 #define CCR 0xE000ED14 // RW Configuration & Control * 15 #define SHPR1 0xE000ED18 // RW System Handler Priority 1 16 #define SHPR2 0xE000ED1C // RW System Handler Priority 2 * 17 #define SHPR3 0xE000ED20 // RW System Handler Priority 3 * 18 #define SHCSR 0xE000ED24 // RW System Handler Control/State * 19 #define CFSR 0xE000ED28 // RW Configurable Fault Status 20 #define DFSR 0xE000ED30 // RW Debug Fault Status * 21 #define HFSR 0xE000ED2C // RW HardFault Status 22 #define MMFAR 0xE000ED34 // RW MemManage Fault Address 23 #define BFAR 0xE000ED38 // RW BusFault Address 24 #define AFSR 0xE000ED3C // RW Aux Fault Status 25 // v6M has only *'d registers 26 27 // DFSR bits indicate debug events, are R/W1C 28 #define DFSR_HALTED 0x00000001 29 #define DFSR_BKPT 0x00000002 30 #define DFSR_DWTTRAP 0x00000004 31 #define DFSR_VCATCH 0x00000008 32 #define DFSR_EXTERNAL 0x00000010 33 34 #define SHCSR_MEMFAULTACT 0x00000001 35 #define SHCSR_BUSFAULTACT 0x00000002 36 #define SHCSR_USGFAULTACT 0x00000008 37 #define SHCSR_SVCALLACT 0x00000080 38 #define SHCSR_MONITORACT 0x00000100 39 #define SHCSR_PENDSVACT 0x00000400 40 #define SHCSR_SYSTICKACT 0x00000800 41 #define SHCSR_USGFAULTPENDED 0x00001000 42 #define SHCSR_MEMFAULTPENDED 0x00002000 43 #define SHCSR_BUSFAULTPENDED 0x00004000 44 #define SHCSR_SVCALLPENDED 0x00008000 // * 45 #define SHCSR_MEMFAULTENA 0x00010000 46 #define SHCSR_BUSFAULTENA 0x00020000 47 #define SHCSR_USGFAULTENA 0x00040000 48 49 #define HFSR_VECTTBL 0x00000002 50 #define HFSR_FORCED 0x40000000 51 #define HFSR_DEBUGEVT 0x80000000 52 53 #define SCR_SLEEPONEXIT 0x00000002 54 #define SCR_SLEEPDEEP 0x00000004 55 #define SCR_SEVONPEND 0x00000010 56 57 #define CCR_NONBASETHRDENA 0x00000001 // Enter Thread Mode w/ Exception Active Enable 58 #define CCR_USESETMPEND 0x00000002 // Unpriv Access to STIR Enable 59 #define CCR_UNALIGN_TRP 0x00000008 // Unaligned Access Trap Enable * 60 #define CCR_DIV_0_TRP 0x00000010 // Divide By Zero Trap Enable 61 #define CCR_BFHFNMIGN 0x00000100 // Ignore Precise Data Faults at Prio -1 & -2 62 #define CCR_STKALIGN 0x00000200 // 8 byte Stack Alignment * 63 #define CCR_DC 0x00010000 // Data & Unified Cache Enable 64 #define CCR_IC 0x00020000 // Instruction Cache Enabel 65 #define CCR_BP 0x00040000 // Branch Prediction Enable 66 67 #define AIRCR_VECTKEY 0x05FA0000 // reads back as 0xFA050000 on v7M 68 #define AIRCR_PRIGROUP_MASK 0x00000700 // 69 #define AIRCR_BIG_ENDIAN 0x00008000 // * 70 #define AIRCR_SYSRESETREQ 0x00000004 // system reset request * 71 #define AIRCR_VECTCLRACTIVE 0x00000002 // clear exception state @ * 72 #define AIRCR_VECTRESET 0x00000001 // request local reset @ 73 74 // @ unpredictable if processor not in debug halt