compiler

commit 171044b77b975fbba1c5c0d3ada8888dc4aca185
parent 04ae1f0ccd34e007569a09105bd7e8b424948257
Author: Brian Swetland <swetland@frotz.net>
Date:   Mon,  6 Dec 2021 06:14:10 -0800

compiler2: share more code for logical ops

Diffstat:
M
src/codegen-risc5-simple.c
 | 
44
+++++++++++---------------------------------

1 file changed, 11 insertions(+), 33 deletions(-)
diff --git a/src/codegen-risc5-simple.c b/src/codegen-risc5-simple.c
@@ -359,46 +359,24 @@ u32 gen_relop(Ast node, u32 cc) {
 	return res;
 }
 
-u32 gen_or_op(Ast node, u32 op) {
+u32 gen_logical_op(Ast node, u32 cc, u32 sc) {
 	u32 r = gen_expr(node->c0);
 	emit_mov(R11, r); // set z flag
 	put_reg(r);
-	u32 l0_br_true = ctx.pc;
-	emit_bi(NE, 0);
+	u32 l0_br_sc = ctx.pc;
+	emit_bi(cc, 0);
 	r = gen_expr(node->c1);
 	emit_mov(R11, r); // set z flag
 	put_reg(r);
-	u32 l1_br_true = ctx.pc;
-	emit_bi(NE, 0);
+	u32 l1_br_sc = ctx.pc;
+	emit_bi(cc, 0);
 	r = get_reg_tmp();
-	emit_movi(r, 0);
+	emit_movi(r, !sc);
 	u32 l2_br_exit = ctx.pc;
 	emit_bi(AL, 0);
-	fixup_branch_fwd(l0_br_true);
-	fixup_branch_fwd(l1_br_true);
-	emit_movi(r, 1);
-	fixup_branch_fwd(l2_br_exit);
-	return r;
-}
-
-u32 gen_and_op(Ast node, u32 op) {
-	u32 r = gen_expr(node->c0);
-	emit_mov(R11, r); // set z flag
-	put_reg(r);
-	u32 l0_br_false = ctx.pc;
-	emit_bi(EQ, 0);
-	r = gen_expr(node->c1);
-	emit_mov(R11, r); // set z flag
-	put_reg(r);
-	u32 l1_br_false = ctx.pc;
-	emit_bi(EQ, 0);
-	r = get_reg_tmp();
-	emit_movi(r, 1);
-	u32 l2_br_exit = ctx.pc;
-	emit_bi(AL, 0);
-	fixup_branch_fwd(l0_br_false);
-	fixup_branch_fwd(l1_br_false);
-	emit_movi(r, 0);
+	fixup_branch_fwd(l0_br_sc);
+	fixup_branch_fwd(l1_br_sc);
+	emit_movi(r, sc);
 	fixup_branch_fwd(l2_br_exit);
 	return r;
 }
@@ -437,9 +415,9 @@ u32 gen_expr(Ast node) {
 		} else if ((op & tcMASK) == tcMULOP) {
 			return gen_binop(node, mul_op_to_ins_tab[op - tSTAR]);
 		} else if (op == tOR) {
-			return gen_or_op(node, op);
+			return gen_logical_op(node, NE, 1);
 		} else if (op == tAND) {
-			return gen_and_op(node, op);
+			return gen_logical_op(node, EQ, 0);
 		} else {
 			error("gen_expr cannot handle binop %s\n", tnames[op]);
 		}