compiler

commit b22576977c02d3f5520abfa753c38482e7f0b2f3
parent a07ff79827100b4ac96a751fbb76844775f60b49
Author: Brian Swetland <swetland@frotz.net>
Date:   Sat,  4 Dec 2021 21:22:57 -0800

emulator: improve trace mode

- don't show memory writes loading program into ram
- make initial register setup display more informative

Diffstat:
M
external/oberon-risc-emu/risc5emu.c
 | 
4
++++
M
external/oberon-risc-emu/risc5emu.h
 | 
1
+
M
src/r5e.c
 | 
30
++++++++++++++++++++----------

3 files changed, 25 insertions(+), 10 deletions(-)
diff --git a/external/oberon-risc-emu/risc5emu.c b/external/oberon-risc-emu/risc5emu.c
@@ -71,6 +71,10 @@ struct RISC *risc_new(bool trace) {
   return risc;
 }
 
+void risc_trace(struct RISC *risc, bool trace) {
+  risc->TRACE = trace;
+}
+
 void risc_reset(struct RISC *risc) {
   risc->PC = 0;
 }
diff --git a/external/oberon-risc-emu/risc5emu.h b/external/oberon-risc-emu/risc5emu.h
@@ -8,6 +8,7 @@ struct RISC *risc_new(bool trace);
 
 void risc_reset(struct RISC *risc);
 void risc_run(struct RISC *risc, int cycles);
+void risc_trace(struct RISC *risc, bool trace);
 
 void risc_single_step(struct RISC *risc);
 void risc_set_register(struct RISC *risc, int reg, uint32_t value);
diff --git a/src/r5e.c b/src/r5e.c
@@ -39,7 +39,7 @@ int main(int argc, char** argv) {
 		return -1;
 	}
 
-	risc_t *r = risc_new(trace);
+	risc_t *r = risc_new(false);
 
 	// load image
 	int fd = open(fn, O_RDONLY);
@@ -59,18 +59,21 @@ int main(int argc, char** argv) {
 
 	// exit shim
 	sp -= 16;
-	risc_store_word(r, sp+0, 0x51000000); // mov r1, 0xffff0000
-	risc_store_word(r, sp+4, 0xa0100100); // stw r0, [r1, 256]
-	risc_store_word(r, sp+8, 0xe7ffffff); // b .
+	uint32_t lr = sp;
+	risc_store_word(r, lr+0, 0x51000000); // mov r1, 0xffff0000
+	risc_store_word(r, lr+4, 0xa0100100); // stw r0, [r1, 256]
+	risc_store_word(r, lr+8, 0xe7ffffff); // b .
 	// point LR at shim
-	risc_set_register(r, 15, sp);
+	risc_set_register(r, 15, lr);
 
 	// r0/r1 is an [][]byte of commandline args
+	uint32_t r0 = 0;
+	uint32_t r1 = 0;
 	if (args) {
 		sp -= args * 8;
 		uint32_t p = sp;
-		risc_set_register(r, 0, p);
-		risc_set_register(r, 1, args);
+		r0 = p;
+		r1 = args;
 		while (args > 0) {
 			fprintf(stderr, "E %s\n", argv[0]);
 			uint32_t n = strlen(argv[0]);
@@ -84,14 +87,21 @@ int main(int argc, char** argv) {
 			args--;
 			argv++;
 		}
-	} else {
-		risc_set_register(r, 0, 0);
-		risc_set_register(r, 1, 0);
 	}
+	risc_set_register(r, 0, r0);
+	risc_set_register(r, 1, r1);
 
 	// set SP
 	risc_set_register(r, 14, sp);
 
+	if (trace) {
+		risc_trace(r, true);
+		printf("                    SP = %08x\n", sp);
+		printf("                    LR = %08x (exit shim)\n", lr);
+		printf("                    R0 = %08x **argv\n", r0);
+		printf("                    R1 = %08x argc\n", r1);
+	}
+
 	do {
 		risc_run(r, 100000000);
 	} while (no_cycle_limit);