cpu32

commit 1c3b287b3efbec89618335aa43a71ee23f74d046
parent c4842146610afee2332a215dc09f627bc41f77ca
Author: Brian Swetland <swetland@frotz.net>
Date:   Fri, 17 Feb 2012 23:36:38 -0800

cpu32: writes to R15 do nothing, so they are never hazards

Diffstat:
M
verilog/cpu32.v
 | 
4
++--

1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/verilog/cpu32.v b/verilog/cpu32.v
@@ -87,8 +87,8 @@ regfile REGS (
 
 // attempt to identify hazards
 wire hazard1, hazard2, hazard_rrw;
-assign hazard1 = (((regs_wsel == opsela) | (regs_wsel == opselb)) & regs_we);
-assign hazard2 = (((mem_wsel == opsela) | (mem_wsel == opselb)) & mem_we);
+assign hazard1 = (((regs_wsel == opsela) | (regs_wsel == opselb)) & regs_we) & (regs_wsel != 4'b1111);
+assign hazard2 = (((mem_wsel == opsela) | (mem_wsel == opselb)) & mem_we) & (mem_wsel != 4'b1111);
 assign hazard_rrw = hazard1 | hazard2;
 
 assign i_addr = pc;