gateware

A collection of little open source FPGA hobby projects
git clone http://frotz.net/git/gateware.git
Log | Files | Refs | README

init.mk (1012B)


      1 ## Copyright 2018 Brian Swetland <swetland@frotz.net>
      2 ##
      3 ## Licensed under the Apache License, Version 2.0 
      4 ## http://www.apache.org/licenses/LICENSE-2.0
      5 
      6 VERILATOR := verilator
      7 NEXTPNR_ICE40 := nextpnr-ice40
      8 NEXTPNR_ECP5 := nextpnr-ecp5
      9 YOSYS := yosys
     10 ICEPACK := icepack
     11 ECPPACK := ecppack
     12 
     13 VIVADOPATH := /work/xilinx/Vivado/2019.2
     14 XSDKPATH := /work/xilinx/SDK/2019.2
     15 
     16 VIVADO := $(VIVADOPATH)/bin/vivado
     17 XELAB := $(VIVADOPATH)/bin/xelab
     18 XSIM := $(VIVADOPATH)/bin/xsim
     19 XMD := $(XSDKPATH)/bin/xmd
     20 
     21 ALL_BUILDS :=
     22 ALL_TARGETS :=
     23 
     24 define project
     25 $(eval PROJECT_DEF := $1)\
     26 $(eval PROJECT_TYPE :=)\
     27 $(eval PROJECT_PART :=)\
     28 $(eval PROJECT_SRCS :=)\
     29 $(eval PROJECT_VOPTS :=)\
     30 $(eval PROJECT_VERILOG_DEFS :=)\
     31 $(eval PROJECT_NEXTPNR_OPTS :=)\
     32 $(eval include $(PROJECT_DEF))\
     33 $(eval PROJECT_NAME := $(patsubst project/%.def,%,$(PROJECT_DEF)))\
     34 $(eval pr-inc := $(wildcard $(patsubst %,build/%.mk,$(PROJECT_TYPE))))\
     35 $(if $(pr-inc),,$(error $1: unknown project type: "$(PROJECT_TYPE)"))\
     36 $(eval include $(pr-inc))
     37 endef
     38