| 2020-02-06 23:16 | cleanup: s/display_timing/display-timing/ | Brian Swetland | 7 | +6 | -6 |
| 2020-02-06 23:10 | build: generate compressed ecp5 bitstreams | Brian Swetland | 1 | +2 | -2 |
| 2020-02-06 23:09 | ulx3s-sdram: setup hdmi display output | Brian Swetland | 3 | +100 | -17 |
| 2020-02-06 23:08 | display: dvi/hdmi backend processing | Brian Swetland | 2 | +200 | -0 |
| 2020-02-05 13:09 | sdram: progressing | Brian Swetland | 13 | +982 | -497 |
| 2020-02-05 02:12 | sdram: simpler/faster memory test (also more colorful) | Brian Swetland | 1 | +72 | -100 |
| 2020-02-05 00:56 | sdram: project to synthesize just the sdram | Brian Swetland | 3 | +127 | -0 |
| 2020-02-05 00:55 | build: pass verilog defines vi PROJECT_VERILOG_DEFS | Brian Swetland | 2 | +3 | -0 |
| 2020-02-04 20:28 | sdram: simpler testbench / stress test | Brian Swetland | 2 | +126 | -305 |
| 2020-02-04 20:19 | sdram: fix off by one in burst length | Brian Swetland | 1 | +12 | -6 |
| 2020-02-04 12:02 | sdram: even more work | Brian Swetland | 6 | +222 | -55 |
| 2020-02-04 11:16 | colorlight-sdram: use 100MHz clock for now | Brian Swetland | 3 | +17 | -3 |
| 2020-02-04 11:15 | async_fifo_one_deep: typo | Brian Swetland | 1 | +1 | -1 |
| 2020-02-01 18:25 | sdram: fancier testbench | Brian Swetland | 6 | +417 | -109 |
| 2020-01-31 12:09 | sdram: more work | Brian Swetland | 2 | +89 | -56 |
| 2020-01-31 06:31 | sdram: more work in progress | Brian Swetland | 5 | +311 | -147 |
| 2020-01-31 06:30 | xorshift: add reset line | Brian Swetland | 2 | +12 | -6 |
| 2020-01-28 15:17 | sdram: hw testing goop for colorlight board | Brian Swetland | 3 | +142 | -0 |
| 2020-01-28 15:15 | sdram: wip mvp sdram controller | Brian Swetland | 4 | +503 | -0 |
| 2020-01-28 15:14 | sim: wip sdram simulation | Brian Swetland | 4 | +348 | -7 |
| 2020-01-27 19:39 | cpu16: move testbench into cpu16 subdir | Brian Swetland | 2 | +1 | -1 |
| 2020-01-26 23:46 | build: deposit simulation logs and traces in out/sim/... | Brian Swetland | 1 | +4 | -2 |
| 2020-01-26 22:29 | sync_fifo_test: tidy this up a bunch | Brian Swetland | 1 | +33 | -131 |
| 2020-01-26 12:35 | async_fifo_one_deep: initial version (untested) | Brian Swetland | 1 | +74 | -0 |
| 2020-01-26 12:29 | sync_fifo: include bypass register by default | Brian Swetland | 1 | +35 | -3 |
| 2020-01-26 12:04 | sync_fifo: simple synchronous fifo 2^N deep | Brian Swetland | 4 | +346 | -0 |
| 2020-01-26 12:01 | colorlight: ethernet experiments continue | Brian Swetland | 3 | +102 | -4 |
| 2020-01-25 23:33 | build: don't dump crctool binary in src | Brian Swetland | 1 | +1 | -1 |
| 2020-01-25 23:31 | build,test: unified test logging, error/exit process | Brian Swetland | 11 | +90 | -66 |
| 2020-01-25 01:58 | testbench: minor cleanup | Brian Swetland | 2 | +10 | -15 |
| 2020-01-24 03:45 | ethernet: add rgmii tx and a debug mode for rx | Brian Swetland | 3 | +267 | -0 |
| 2020-01-23 02:22 | ethernet: rgmii rx and colorlight demo project | Brian Swetland | 6 | +392 | -0 |
| 2020-01-23 02:22 | display: check in simulator test | Brian Swetland | 2 | +39 | -1 |
| 2020-01-23 00:54 | ethernet: move testdata into hdl/ethernet/ as well | Brian Swetland | 2 | +1 | -1 |
| 2020-01-23 00:21 | new readme | Brian Swetland | 1 | +16 | -0 |
| 2020-01-23 00:14 | arty: use new display | Brian Swetland | 1 | +20 | -1 |
| 2020-01-23 00:12 | ethernet: move stuff under hdl/ethernet | Brian Swetland | 5 | +2 | -1 |
| 2020-01-23 00:06 | cpu16: migrate most cpu16 stuff to hdl/cpu16 | Brian Swetland | 10 | +6 | -5 |
| 2020-01-23 00:06 | testbench.cpp: minor tweaks | Brian Swetland | 1 | +10 | -2 |
| 2020-01-22 23:53 | display: add HEXMODE to display vram as hex bytes | Brian Swetland | 1 | +53 | -7 |
| 2020-01-18 21:16 | display: rgb mode | Brian Swetland | 2 | +43 | -6 |
| 2020-01-18 20:24 | display: fix bugs | Brian Swetland | 3 | +52 | -40 |
| 2020-01-17 01:51 | display: new vga/hdmi display and associated projects | Brian Swetland | 10 | +9234 | -1 |
| 2020-01-11 12:23 | xilinx: add synthesis builds using vivado and a test project | Brian Swetland | 9 | +482 | -0 |
| 2020-01-11 11:41 | ecp5: build rules and test project for ecp5-evn board | Brian Swetland | 6 | +216 | -0 |
| 2020-01-08 08:36 | cleanup: verilog correctness | Brian Swetland | 12 | +396 | -394 |
| 2020-01-05 02:37 | testvga: fix build | Brian Swetland | 1 | +1 | -1 |
| 2018-12-27 04:02 | icebreaker diagnostics project | Brian Swetland | 3 | +78 | -0 |
| 2018-12-19 01:22 | vga40x30: add new "full rgb" mode | Brian Swetland | 3 | +44 | -15 |
| 2018-12-18 22:35 | vga40x30: fix cdata and pdata preloading | Brian Swetland | 2 | +59 | -26 |
| 2018-12-18 00:18 | eth_rmii_rx.sv: ethernet rmii packet receiver block | Brian Swetland | 1 | +200 | -0 |
| 2018-12-18 00:17 | eth_crc32_*: 32bit crc for ethernet fcs | Brian Swetland | 5 | +334 | -0 |
| 2018-12-18 00:04 | crctool: generate verilog for crc blocks | Brian Swetland | 2 | +155 | -1 |
| 2018-12-15 16:17 | cleanup: add `default_nettype none to all verilog sources | Brian Swetland | 21 | +42 | -0 |
| 2018-12-15 16:02 | project: add cpu16-icebreaker-hdmi111 project | Brian Swetland | 8 | +111 | -0 |
| 2018-12-15 13:54 | cleanup: remove old uart module | Brian Swetland | 1 | +0 | -76 |
| 2018-12-15 13:53 | udebug: update cpu16-icebreaker/lattice-evb to use udebug | Brian Swetland | 6 | +40 | -3 |
| 2018-12-15 13:50 | udebug: uart debug interface, hdl and commandline tool | Brian Swetland | 6 | +624 | -1 |
| 2018-12-09 16:43 | cleanup: make things tidier | Brian Swetland | 13 | +385 | -289 |
| 2018-12-08 19:29 | build: overhaul the build system | Brian Swetland | 8 | +184 | -82 |
| 2018-12-05 05:58 | cpu16: fiddle with sram definition | Brian Swetland | 1 | +14 | -5 |
| 2018-12-03 22:47 | cpu16: some more alu tests | Brian Swetland | 2 | +42 | -0 |
| 2018-12-03 07:25 | cleanup: remove obsolete assemblers | Brian Swetland | 4 | +0 | -1724 |
| 2018-12-03 07:06 | cleanup: remove old v3 cpu impl and v3/v4 isa docs | Brian Swetland | 5 | +0 | -573 |
| 2018-12-02 00:32 | cpu16: switch over to isa v5, add/update tests, tidy up | Brian Swetland | 12 | +557 | -380 |
| 2018-12-01 00:26 | isa16v5: new assembler and disassembler | Brian Swetland | 3 | +919 | -12 |
| 2018-11-30 22:11 | cpu16: move legacy isa docs to docs dir | Brian Swetland | 1 | +0 | -0 |
| 2018-11-30 22:08 | cpu16: yet another ISA revision | Brian Swetland | 1 | +39 | -0 |
| 2018-11-28 22:59 | cpu16: support memory write, implement writeback stage | Brian Swetland | 2 | +48 | -14 |
| 2018-11-28 21:26 | cpu16: stall during register conflicts | Brian Swetland | 1 | +13 | -8 |
| 2018-11-28 20:34 | cpu16: stall after branches | Brian Swetland | 1 | +59 | -21 |
| 2018-11-28 17:57 | cpu16: conditional branches and branch with link | Brian Swetland | 3 | +17 | -7 |
| 2018-11-28 17:56 | ice40: fix ins ram bug, tidy up | Brian Swetland | 1 | +21 | -34 |
| 2018-11-28 04:16 | cpu16: optional 64bit trace port | Brian Swetland | 1 | +27 | -0 |
| 2018-11-28 04:13 | scope: a 64bit x 16Ksample "logic analyzer" | Brian Swetland | 1 | +188 | -0 |
| 2018-11-27 02:43 | cpu16: ensure registers use bram, fix lw/sw offsets | Brian Swetland | 2 | +67 | -1 |
| 2018-11-27 00:06 | build: default to using nextpnr for p&r | Brian Swetland | 1 | +1 | -1 |
| 2018-11-25 23:20 | ice40: add WITH_CPU define | Brian Swetland | 1 | +10 | -0 |
| 2018-11-25 22:56 | ice40 tweaks | Brian Swetland | 2 | +10 | -2 |
| 2018-11-25 22:22 | cpu16/ice40: tweak verilog to make icecube/synplify happy | Brian Swetland | 2 | +21 | -15 |
| 2018-11-25 06:44 | tests: update for cpu16v4 | Brian Swetland | 12 | +134 | -100 |
| 2018-11-25 06:46 | cpu16: cpu16v4 work in progress | Brian Swetland | 5 | +441 | -70 |
| 2018-11-25 07:44 | a16/d16: use the "true" nop rather than the alu nop | Brian Swetland | 2 | +7 | -5 |
| 2018-11-25 06:43 | a16: add halt pseudo-op | Brian Swetland | 1 | +5 | -2 |
| 2018-11-24 22:17 | d16: improve disassembly filter | Brian Swetland | 1 | +18 | -17 |
| 2018-11-24 18:35 | isa: some notes on possible changes | Brian Swetland | 1 | +9 | -0 |
| 2018-11-24 01:45 | isa16v4: rethink the instruction set architecture | Brian Swetland | 4 | +926 | -0 |
| 2018-11-22 03:20 | vga: rework most of this | Brian Swetland | 4 | +92 | -161 |
| 2018-11-21 21:04 | build: build a vga testbench if you 'make vga' | Brian Swetland | 3 | +64 | -11 |
| 2018-11-21 21:01 | vga: expose frame sync signal for use in testbenches | Brian Swetland | 3 | +16 | -6 |
| 2018-11-21 20:59 | testbench: add vga frame extractor | Brian Swetland | 1 | +76 | -2 |
| 2018-11-20 20:26 | vga: tidy up a bunch, fix synthesis in vivado | Brian Swetland | 5 | +83 | -58 |
| 2018-11-20 10:52 | icetool: add -cls command to clear the framebuffer | Brian Swetland | 1 | +18 | -3 |
| 2018-11-20 10:51 | build: support nextpnr as well as arachne-pnr | Brian Swetland | 1 | +14 | -1 |
| 2018-11-19 07:08 | cpu: shuffle some names around for a bit more clarity | Brian Swetland | 1 | +16 | -7 |
| 2018-11-19 01:49 | tidying up a bit | Brian Swetland | 7 | +69 | -10 |
| 2018-11-18 19:32 | build fixes | Brian Swetland | 3 | +18 | -2 |
| 2018-11-17 20:13 | hack: make vga background red when cpu is held in reset | Brian Swetland | 1 | +10 | -3 |
| 2018-11-17 19:42 | vga: provide dedicated videoram write clock | Brian Swetland | 3 | +14 | -5 |
| 2018-11-17 19:35 | support building for ice40up5k dev board w/ icestorm | Brian Swetland | 5 | +97 | -57 |
| 2018-11-17 18:57 | chardata: correctly init state machine state | Brian Swetland | 1 | +2 | -2 |
| 2018-11-17 17:29 | icetool: accept /blahblah to write ascii instead of hex | Brian Swetland | 1 | +10 | -2 |
| 2018-11-16 03:17 | update for latest verilator | Brian Swetland | 2 | +3 | -3 |
| 2015-12-31 04:40 | cleanup, lint fixes, etc | Brian Swetland | 4 | +35 | -11 |
| 2015-12-31 04:07 | updated top file, constrains and pll config for ICE40Ultra dev board | Brian Swetland | 4 | +158 | -28 |
| 2015-12-31 04:06 | update for reset | Brian Swetland | 1 | +2 | -1 |
| 2015-12-31 04:05 | spi debug interface -- allows for download to ram via spi | Brian Swetland | 1 | +157 | -0 |
| 2015-12-31 04:03 | vga character display from my old cpu32 project | Brian Swetland | 6 | +3394 | -0 |
| 2015-12-31 04:03 | add reset to cpu | Brian Swetland | 1 | +11 | -4 |
| 2015-12-31 02:43 | icetool: download data to target fpga over SPI (via FTDI MSSPE) | Brian Swetland | 4 | +408 | -1 |
| 2015-12-31 02:43 | debug nop support | Brian Swetland | 1 | +11 | -0 |
| 2015-12-30 09:02 | define a DEBUG instruction in the NOP instruction space | Brian Swetland | 3 | +16 | -2 |
| 2015-12-30 08:33 | cpu: fix parameterization for 32bit regs configuration | Brian Swetland | 1 | +5 | -4 |
| 2015-12-30 06:58 | last traces of the previous condition-register-having design | Brian Swetland | 2 | +1 | -39 |
| 2015-12-30 06:51 | update ISA document | Brian Swetland | 1 | +41 | -36 |
| 2015-12-30 06:27 | add a readme | Brian Swetland | 1 | +32 | -0 |
| 2015-12-30 06:10 | make test target and some tests | Brian Swetland | 4 | +88 | -0 |
| 2015-12-30 05:56 | some support for a test infrastructure | Brian Swetland | 6 | +54 | -47 |
| 2015-12-30 05:55 | fix using flags for opcode B imm12 | Brian Swetland | 1 | +1 | -0 |
| 2015-12-30 05:55 | remove cruft | Brian Swetland | 1 | +0 | -19 |
| 2015-12-30 04:55 | cpu16: fix using mask for MHI operation | Brian Swetland | 1 | +1 | -1 |
| 2015-12-30 04:55 | testbench: 64K words memory to avoid clobbering | Brian Swetland | 2 | +6 | -4 |
| 2015-12-30 04:37 | Tweak verilator driver to have the first +clk at 10ns | Brian Swetland | 1 | +8 | -0 |
| 2015-12-30 04:23 | rework all sorts of things | Brian Swetland | 12 | +467 | -900 |
| 2015-12-28 10:41 | pipelined variant of cpu16 | Brian Swetland | 1 | +378 | -0 |
| 2015-12-28 07:45 | set aside reset logic for now | Brian Swetland | 1 | +4 | -4 |
| 2015-12-27 11:09 | initial | Brian Swetland | 22 | +2061 | -0 |
