arty_a7_hdmi111.sv (1011B)
1 2 `default_nettype none 3 4 module top( 5 input wire clk, 6 input wire [3:0]btn, 7 output wire hdmi_r, 8 output wire hdmi_g, 9 output wire hdmi_b, 10 output wire hdmi_hs, 11 output wire hdmi_vs, 12 output wire hdmi_ck, 13 output wire hdmi_de, 14 output reg [3:0]led 15 ); 16 17 wire clk25m; 18 19 assign hdmi_ck = clk25m; 20 21 mmcm_100m_25m pll( 22 .clk100m_i(clk), 23 .clk25m_o(clk25m) 24 ); 25 26 always_ff @(posedge clk25m) begin 27 led[0] <= btn[0]; 28 led[1] <= btn[1]; 29 led[2] <= btn[2]; 30 led[3] <= btn[3]; 31 end 32 33 `ifdef OLDECODE 34 vga40x30x2 #( 35 .BPP(1), 36 .RGB(0) 37 )hdmi( 38 .clk25m(clk25m), 39 .red(hdmi_r), 40 .grn(hdmi_g), 41 .blu(hdmi_b), 42 .hs(hdmi_hs), 43 .vs(hdmi_vs), 44 .fr(), 45 .active(hdmi_de), 46 .vram_clk(clk25m), 47 .vram_waddr(0), 48 .vram_wdata(0), 49 .vram_we(0) 50 ); 51 `else 52 display #( 53 .BPP(1) 54 ) display0 ( 55 .clk(clk25m), 56 .red(hdmi_r), 57 .grn(hdmi_g), 58 .blu(hdmi_b), 59 .hsync(hdmi_hs), 60 .vsync(hdmi_vs), 61 .active(hdmi_de), 62 .frame(), 63 .wclk(clk25m), 64 .waddr(0), 65 .wdata(0), 66 .we(0) 67 ); 68 `endif 69 70 endmodule