board_icebreaker_hdmi111.v (1182B)
1 // Copyright 2018, Brian Swetland <swetland@frotz.net> 2 // Licensed under the Apache License, Version 2.0. 3 4 `default_nettype none 5 6 module top( 7 input clk12m_in, 8 output hdmi_red, 9 output hdmi_grn, 10 output hdmi_blu, 11 output hdmi_hsync, 12 output hdmi_vsync, 13 output hdmi_de, 14 output hdmi_clk, 15 input uart_rx, 16 output uart_tx, 17 output led_red, 18 output led_grn 19 ); 20 21 wire hdmi_clk_src; 22 23 `ifdef verilator 24 assign hdmi_clk = hdmi_clk_src; 25 `else 26 SB_IO #( 27 .PIN_TYPE(6'b010000), // DDR OUTPUT 28 .PULLUP(1'b0), 29 .NEG_TRIGGER(1'b0), 30 .IO_STANDARD("SB_LVCMOS") 31 ) hdmi_clk_io ( 32 .PACKAGE_PIN(hdmi_clk), 33 .LATCH_INPUT_VALUE(), 34 .CLOCK_ENABLE(), // per docs, leave discon for always enable 35 .INPUT_CLK(), 36 .OUTPUT_CLK(hdmi_clk_src), 37 .D_OUT_0(1'b1), 38 .D_OUT_1(1'b0), 39 .D_IN_0(), 40 .D_IN_1() 41 ); 42 `endif 43 44 system_cpu16_vga40x30 #( 45 .BPP(1) 46 ) system ( 47 .clk12m_in(clk12m_in), 48 .vga_red(hdmi_red), 49 .vga_grn(hdmi_grn), 50 .vga_blu(hdmi_blu), 51 .vga_hsync(hdmi_hsync), 52 .vga_vsync(hdmi_vsync), 53 .vga_active(hdmi_de), 54 .vga_clk(hdmi_clk_src), 55 .spi_mosi(), 56 .spi_miso(), 57 .spi_clk(), 58 .spi_cs(), 59 .uart_rx(uart_rx), 60 .uart_tx(uart_tx), 61 .led_red(led_red), 62 .led_grn(led_grn), 63 .out1(), 64 .out2() 65 ); 66 67 endmodule