colorlight-sdram.sv (2672B)
1 // Copyright 2020, Brian Swetland <swetland@frotz.net> 2 // Licensed under the Apache License, Version 2.0. 3 4 `default_nettype none 5 6 module top( 7 input wire phy_clk, 8 9 output sdram_clk, 10 output sdram_ras_n, 11 output sdram_cas_n, 12 output sdram_we_n, 13 output [11:0]sdram_addr, 14 inout [15:0]sdram_data, 15 16 output wire glb_clk, 17 output wire glb_bln, 18 output wire j1r0, 19 output wire j1r1, 20 output wire j1g0, 21 output wire j1g1, 22 output wire j1b0, 23 output wire j1b1, 24 output wire glb_a, 25 output wire glb_b, 26 input wire btn 27 ); 28 29 wire clk25m = phy_clk; 30 31 `define CLK125 32 `ifdef CLK125 33 wire clk125m; 34 wire clk250m; 35 36 pll_25_125_250 pll( 37 .clk25m_in(phy_clk), 38 .clk125m_out(clk125m), 39 .clk250m_out(clk250m), 40 .locked() 41 ); 42 `else 43 wire clk100m; 44 45 pll_25_100 pll( 46 .clk25m_in(phy_clk), 47 .clk100m_out(clk100m), 48 .locked() 49 ); 50 `endif 51 52 wire testclk = clk125m; 53 54 wire [19:0]rd_addr; 55 wire [15:0]rd_data; 56 wire [3:0]rd_len; 57 wire rd_req; 58 wire rd_ack; 59 wire rd_rdy; 60 61 wire [19:0]wr_addr; 62 wire [15:0]wr_data; 63 wire wr_req; 64 wire wr_ack; 65 wire [3:0]wr_len; 66 67 wire [15:0]info; 68 wire info_e; 69 70 testbench #( 71 .BANKBITS(1), 72 .ROWBITS(11), 73 .COLBITS(8) 74 ) test0 ( 75 .clk(testclk), 76 .error(), 77 .done(), 78 79 .rd_addr(rd_addr), 80 .rd_data(rd_data), 81 .rd_len(rd_len), 82 .rd_req(rd_req), 83 .rd_ack(rd_ack), 84 .rd_rdy(rd_rdy), 85 86 .wr_addr(wr_addr), 87 .wr_data(wr_data), 88 .wr_len(wr_len), 89 .wr_req(wr_req), 90 .wr_ack(wr_ack), 91 92 .info(info), 93 .info_e(info_e) 94 ); 95 96 sdram #( 97 .BANKBITS(1), 98 .ROWBITS(11), 99 .COLBITS(8), 100 .T_PWR_UP(25000), 101 .T_RI(1900), 102 .T_RCD(3), 103 .CLK_SHIFT(1), 104 .CLK_DELAY(0) 105 ) sdram0 ( 106 .clk(testclk), 107 .reset(0), 108 109 .pin_clk(sdram_clk), 110 .pin_ras_n(sdram_ras_n), 111 .pin_cas_n(sdram_cas_n), 112 .pin_we_n(sdram_we_n), 113 .pin_addr(sdram_addr), 114 .pin_data(sdram_data), 115 116 `ifdef SWIZZLE 117 .rd_addr({rd_addr[7:4],rd_addr[19:8],rd_addr[3:0]}), 118 .wr_addr({wr_addr[7:4],wr_addr[19:8],wr_addr[3:0]}), 119 `else 120 .rd_addr(rd_addr), 121 .wr_addr(wr_addr), 122 `endif 123 124 .rd_data(rd_data), 125 .rd_len(rd_len), 126 .rd_req(rd_req), 127 .rd_ack(rd_ack), 128 .rd_rdy(rd_rdy), 129 130 .wr_data(wr_data), 131 .wr_len(wr_len), 132 .wr_req(wr_req), 133 .wr_ack(wr_ack) 134 ); 135 136 137 assign j1r1 = j1r0; 138 assign j1b1 = j1b0; 139 assign j1g1 = j1g0; 140 141 reg [10:0]waddr = 11'd0; 142 143 wire [10:0]waddr_next = (waddr == 11'd1199) ? 11'd0 : (waddr + 11'd1); 144 145 always_ff @(posedge testclk) begin 146 waddr <= (info_e) ? waddr_next : waddr; 147 end 148 149 display #( 150 .BPP(1), 151 .RGB(1), 152 .WIDE(0), 153 .HEXMODE(1) 154 ) display0 ( 155 .clk(clk25m), 156 .red(j1r0), 157 .grn(j1g0), 158 .blu(j1b0), 159 .hsync(glb_a), 160 .vsync(glb_b), 161 .active(), 162 .frame(), 163 .wclk(testclk), 164 .waddr({waddr,1'b0}), 165 .wdata(info), 166 .we(info_e) 167 ); 168 169 endmodule 170