colorlight.sv (3138B)
1 `default_nettype none 2 3 module top( 4 input wire phy_clk, 5 output wire phy_reset_n, 6 7 input wire phy0_rxc, 8 input wire [3:0]phy0_rxd, 9 input wire phy0_rx_dv, 10 11 output wire phy1_gtxclk, 12 output wire phy1_tx_en, 13 output wire [3:0]phy1_txd, 14 15 output wire glb_clk, 16 output wire glb_bln, 17 output wire j1r0, 18 output wire j1r1, 19 output wire j1g0, 20 output wire j1g1, 21 output wire j1b0, 22 output wire j1b1, 23 output wire glb_a, 24 output wire glb_b, 25 input wire btn 26 ); 27 28 wire clk25m = phy_clk; 29 30 wire clk125m; 31 wire clk250m; 32 33 pll_25_125_250 pll( 34 .clk25m_in(phy_clk), 35 .clk125m_out(clk125m), 36 .clk250m_out(clk250m), 37 .locked() 38 ); 39 40 `ifdef XXX 41 reg [31:0]count1; 42 always_ff @(posedge phy1_rxc) begin 43 count1 <= count1 + 32'd1; 44 end 45 assign glb_clk = count1[1]; 46 47 reg [31:0]count0; 48 always_ff @(posedge phy0_rxc) begin 49 count0 <= count0 + 32'd1; 50 end 51 assign glb_bln = count0[1]; 52 `endif 53 54 wire tx_clk = clk125m; 55 reg tx_start = 0; 56 reg tx_valid = 0; 57 reg tx_error = 0; 58 reg [7:0]tx_data = 8'd0; 59 wire tx_ready; 60 61 eth_rgmii_tx eth_tx( 62 .tx_clk(tx_clk), 63 .pin_tx_clk(phy1_gtxclk), 64 .pin_tx_en(phy1_tx_en), 65 .pin_tx_data(phy1_txd), 66 .start(tx_start), 67 .ready(tx_ready), 68 .valid(tx_valid), 69 .error(tx_error), 70 .data(tx_data) 71 ); 72 73 74 reg [7:0]msgram[0:63]; 75 76 initial $readmemh("hdl/message.hex", msgram); 77 78 79 reg [31:0]count1s = 32'd0; 80 always_ff @(posedge tx_clk) begin 81 if (count1s == 32'd125000000) begin 82 count1s <= 32'd0; 83 tx_start <= 1; 84 end else begin 85 count1s <= count1s + 32'd1; 86 tx_start <= 0; 87 end 88 end 89 90 reg [7:0]xcount = 8'd0; 91 reg [7:0]next_xcount; 92 reg next_tx_valid; 93 reg [7:0]next_tx_data; 94 95 always_comb begin 96 next_xcount = xcount; 97 next_tx_valid = tx_valid; 98 next_tx_data = xcount; 99 100 if (tx_start) begin 101 next_tx_valid = 1; 102 next_xcount = 8'd0; 103 end 104 105 if (tx_valid & tx_ready) begin 106 if (xcount < 8'd64) begin 107 next_xcount = xcount + 8'd1; 108 end else begin 109 next_tx_valid = 0; 110 end 111 end 112 end 113 114 always_ff @(posedge tx_clk) begin 115 xcount <= next_xcount; 116 tx_valid <= next_tx_valid; 117 tx_data <= msgram[next_xcount[5:0]]; 118 end 119 120 wire [7:0]rx_data; 121 wire rx_valid; 122 wire rx_sop; 123 wire rx_eop; 124 wire rx_crc_ok; 125 126 eth_rgmii_rx eth_rx( 127 .rx_clk(phy0_rxc), 128 .pin_rx_dv(phy0_rx_dv), 129 .pin_rx_data(phy0_rxd), 130 .data(rx_data), 131 .valid(rx_valid), 132 .sop(rx_sop), 133 .eop(rx_eop), 134 .crc_ok(rx_crc_ok) 135 ); 136 137 assign j1r1 = j1r0; 138 assign j1b1 = j1b0; 139 assign j1g1 = j1g0; 140 141 reg [31:0]reset = 32'd0; 142 always @(posedge clk25m) 143 reset <= { reset[30:0], 1'b1 }; 144 145 assign phy_reset_n = reset[31]; 146 147 reg [11:0]waddr = 12'd0; 148 149 reg [27:0]color = 28'h1234567; 150 151 always_ff @(posedge phy0_rxc) begin 152 color <= rx_eop ? { color[23:0], color[27:24] } : color; 153 waddr <= (rx_eop | rx_valid) ? (waddr + 12'd2) : waddr; 154 end 155 156 wire [15:0]mark = rx_crc_ok ? { 16'h0200 } : { 16'h04FF }; 157 158 display #( 159 .BPP(1), 160 .RGB(1), 161 .WIDE(0), 162 .HEXMODE(1) 163 ) display0 ( 164 .clk(clk25m), 165 .red(j1r0), 166 .grn(j1g0), 167 .blu(j1b0), 168 .hsync(glb_a), 169 .vsync(glb_b), 170 .active(), 171 .frame(), 172 .wclk(phy0_rxc), 173 .waddr(waddr), 174 .wdata(rx_eop ? mark : { color[27:24], 4'h0, rx_data }), 175 .we((rx_eop | rx_valid) & btn) 176 ); 177 178 endmodule 179