README (1308B)
1 2 CPU16 is a 16-bit-instruction, 16 register, RISC-ish CPU 3 -------------------------------------------------------- 4 5 My goal is something that in the minimal configuration would fit on 6 a tiny FPGA like the low end of the Lattice ICE40 series (~1000 LUTs 7 and FFs), leave some room for peripherals, be relatively simple but 8 featureful enough that targeting a C compiler at it would make sense. 9 10 At the moment the small configuration is weighing in at about 500-600 11 LUTs and 120-130 FFs. It's not quite done yet, not fully debugged, 12 and there's probably some room for optimization still. Hopefully it 13 will not get significantly larger and maybe it'll get smaller. 14 15 A small assembler (a16) is included, along with a small (but growing) 16 set of assembly test cases. Infrastructure for automated testing on 17 a FPGA dev board (in addition to automated testing in simulation) is 18 in the works. 19 20 Verilator is used for simulation. 21 22 Optional/Future Features (in progress) 23 - fancier ALU (full barrel shifters + ~120 LUTs) 24 - 32bit registers (vs 16bit) 25 - pipeline bypass (instead of stalling on conflicts) 26 - extended instruction set: 27 IRQs, Control Registers, Register Banks, Syscalls 28 - C Compiler (TCC? LLVM? Hacky homebrew thing?) 29 30 31 Instruction Set Details: 32 https://github.com/swetland/cpu16/blob/master/hdl/cpu/isa.txt